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WICED Studio Wi-Fi Combo

New Contributor

Good afternoon, WICED community!

I have a question about the CYW43907 chip and GSIO SPI master interface.

I want to stream the data from SPI slave and send it in a form of UDP packages to Wi-Fi.

I am using WICED Studio 6.4 to read the data from the SPI slave as fast as possible. However, I have noticed that the GSIO driver works in polling mode that increases CPU usage. Moreover, I can see the inter-byte delays and the delays caused by manually toggled CS line.

They equal about 0.8 microseconds for both inter-byte and chip select delay. Please, receive the waveform with the 5 MHz clock signal and CS signal captured by the oscilloscope.

inter_byte_delay.jpgcs_delay.jpg

The code I am using to send the SPI packets is the following:

wiced_result_t spi_send(uint8_t *tx_buf_ptr, uint8_t *rx_buf_ptr, int size, wiced_spi_device_t *spi_device_ptr)

{

   platform_result_t result   = PLATFORM_SUCCESS;

   platform_spi_config_t config;

   /* Chip select is not a GPIO when NULL. */

   config.chip_select = ( spi_device_ptr->chip_select != WICED_GPIO_NONE ) ? &platform_gpio_pins[spi_device_ptr->chip_select] : NULL;

   config.speed   = spi_device_ptr->speed;

   config.mode   = spi_device_ptr->mode;

   config.bits   = spi_device_ptr->bits;

   /* Activate chip select */

   platform_spi_chip_select_toggle(&platform_spi_peripherals[spi_device_ptr->port], &config, WICED_TRUE );

   /* SPI transfer after init and CS */

   platform_spi_transfer_nosetup( &platform_spi_peripherals[spi_device_ptr->port], &config, tx_buf_ptr, rx_buf_ptr, size);

   /* Deassert chip select */

   platform_spi_chip_select_toggle(&platform_spi_peripherals[spi_device_ptr->port], &config, WICED_FALSE );

   return (wiced_result_t) result;

}

It is a modified version of wiced_spi_transfer function that eliminates multiple SPI initialization (with the original function the delay between the packages is too big)

Given the results above, I have the following questions:

1. Is it possible to use SPI GSIO Master in interrupt or DMA mode?
The polling mode seems to be slow.

2. How can I decrease inter-byte distance and chip select delay in polling mode?

3. What is the maximum SPI GSIO Master clock frequency and corresponding data transfer rate tested by Cypress engineers?

4. Is it possible to increase the slew rate of SPI  GPIO pins to increase the signal quality?

5. Does the next generation CYW54907 WiFI MCU has the same SPI GSIO functionality and bugs or did Cypress engineers improved the module?

Thank you in advance.

Best,

Sergei

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1 Solution
Moderator
Moderator

Hi Sergei

Thanks for all the effort you took in providing me with the plots

From the plots, I can understand the inter-byte delay is caused by the polling mechanism.

We cannot do much here to avoid the delay as this is hardware specific thing.

The driver code is as follows:

1. gsio_regs[spi->port].interface->data = data;  --> The data is being fetch to the GSIO register

2. gsio_regs[spi->port].interface->ctrl |= GSIO_SB_BUSY;  -->  The GSIO start busy bit will be set (this will cause some delay - I suspect that 414 nano second)

3. gsio_wait_for_xfer_to_complete( spi->port ); --> GSIO will wait for transfer to complete i.e. polling will take place and hence the maximum inter-byte delay takes place

The above is a driver code which is been written as per the hardware algorithm and hence I said we cannot do much about it.

I hope this solves your doubt related to inter-byte delay.

Regarding the slew rate: I need to ask the internal team and will get back to you on this once I have a proper explanation about it.

Thanks and regards

View solution in original post

10 Replies
Moderator
Moderator

Hi

Q1: Is it possible to use SPI GSIO Master in interrupt or DMA mode?

A: Actually, you cannot use SPI over DMA. You can have a look at this thread Re: Is there any example where it uses DMA SPI? and also the blog post for your reference SPI in CYW43907

Q2: How can I decrease inter-byte distance and chip select delay in polling mode?

A: I am not clear with the oscilloscope waveforms you have sent. Can you please elaborate more on:

1. In figure 1: What is the data pattern being sent (I can see 1010 1010) ? What does the 2nd line/plot indicates?

2. In figure 2: Again, what is the data pattern (I can see 1010 0000)? Also, what are the readings for both the plots?

Q3: What is the maximum SPI GSIO Master clock frequency and corresponding data transfer rate tested by Cypress engineers?

A: According to datasheet, it's 40MHz

Q4: Is it possible to increase the slew rate of SPI  GPIO pins to increase the signal quality?

A: Please let me know whether you are using CYW943907EVAL1F evaluation board or your own custom board ?

Q5: Does the next generation CYW54907 WiFI MCU has the same SPI GSIO functionality and bugs or did Cypress engineers improved the module?

A: Yes, both have same SPI GSIO functionality.

Thanks and regards

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New Contributor

Thank you for the answers. Please, find below some clarifications from my side:

Q2: How can I decrease inter-byte distance and chip select delay in polling mode?

"

A: I am not clear with the oscilloscope waveforms you have sent. Can you please elaborate more on:

1. In figure 1: What is the data pattern being sent (I can see 1010 1010) ? What does the 2nd line/plot indicates?

2. In figure 2: Again, what is the data pattern (I can see 1010 0000)? Also, what are the readings for both the plots?

"

Both plots show SPI clock (yellow) and SPI Chip select signals (green). Please, receive annotated screenshots below.

P.S. Please, don't be confused by Y axis scaling. Both channels 1 and 2 have 10:1 dividers that I didn't specify in the oscilloscope settings. In reality the signal levels were fine (3.3 V)

Untitled.jpeg

Untitled (1).jpeg

I cannot tell you which data was presented on MISO and MOSI lines because I didn't capture these lines during the measurements. Regardless of the values I sent, I always observed the delays highlighted above.

Q4: Is it possible to increase the slew rate of SPI  GPIO pins to increase the signal quality?

"A: Please let me know whether you are using CYW943907EVAL1F evaluation board or your own custom board ?"

Now I am using CYW943907EVAL1F evaluation board. In the nearest future I will design a custom board.

Thank you in advance.

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Moderator
Moderator

Hi

Correct me if I am wrong, the 2nd image is the zoomed (X-axis - time/div) version of 1st, right?

And, in figure 2, what does the small pulse indicates (in between chip select delays)? Is it the chip select toggle?

Thanks

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New Contributor

Hello,

Both images have the same timescale. Yes, the green signal pulse is chip select toggle. Let me provide a short explanation.

I am sending SPI packages of 2 bytes from SPI master (Cypress chip) continuously one after another. The CS line goes low and initiates the transmission. I am going to send 2 bytes.

Here I captured the figure 1 where CS signal is active (low) and you can see 2 trains of 8 clock pulses separated by inter-byte delay.

Ideally, I want to see one single train of 16 pulses. Instead, there is a delay. I am asking, how to minimize such a delay.

Then, after I transmitted the last byte, the transmission is completed and CS signal goes high (not active). It doesn't go high immediately, but after chip select delay.  That is what you can see in the figure 2.

Finally, I  wait for a while and start a new transaction, CS goes low again and after some delay (I called chip select delay too) the SPI hardware starts the transmission.

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New Contributor

Good morning,

You said:

"Q3: What is the maximum SPI GSIO Master clock frequency and corresponding data transfer rate tested by Cypress engineers?

A: According to datasheet, it's 40MHz"

Indeed, the datasheet states 40 MHz as a maximum frequency. But is it even possible? I tried to measure the SPI Clock signal rise time for different loads (10k, 100k, open circuit). I am always getting the rise time that is about 20ns (see the figure below)

img_20201130_193909.459 (1).jpg

Then, we can estimate the maximum frequency as 0.35/(rise time). For 20 ns rise time, the maximum estimated frequency will be about  17.5 MHz that is far below the 40 MHz mentioned in the datasheet.

1. Could you, please, confirm that Cypress team obtains the same results for the rise time of SPI Clock pins?

2. Are these values expected or not?

Thank you in advance.

Best,

Sergei

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Moderator
Moderator

Hi

Can you please perform a small test (mentioned below) to understand the inter-byte delay issue?

Things to do:

1. To check the overall delay, switch on and off one of the on-board LED inside the spi_transfer_nosetup() function in such fashion:

static platform_result_t spi_transfer_nosetup( **arguments** )

//other code

led_on();

gsio_wait_for_xfer_to_complete( spi->port );

led_off();

//other_code

}

2. Check the toggling on the oscilloscope and plot all the 3 graphs (data, CS, LED) one below the other and please send it.

We might get a clear picture of the delay by performing this.

Regarding the slew rate: Please let me know on which pin you are testing the slew rate (data/ clock/ CS).

Thanks

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New Contributor

Hello,

Yes, sure. I will do the test a bit later and then share the results with you.

Regrading the pin, I measured slew rate on SPI_0_CLOCK signal routed to J6.12 connector of the CYW943907EVAL1F PCB.

Best,

Sergei

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New Contributor

Hello,

I completed the test you asked for.

I used the following code below:

static platform_result_t spi_transfer_nosetup( **arguments** ){

        //other code

        platform_led_set_state(0, 1);

        gsio_wait_for_xfer_to_complete( spi->port );

        platform_led_set_state(0, 0);

        //other_code

}

Please, see the waveforms below:

1.jpg2.jpg3.jpg4.jpg5.jpg6.jpg7.jpg8.jpg9.jpg

By the way, do you have any updates about slew rate?

Best,

Sergei

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Moderator
Moderator

Hi Sergei

Thanks for all the effort you took in providing me with the plots

From the plots, I can understand the inter-byte delay is caused by the polling mechanism.

We cannot do much here to avoid the delay as this is hardware specific thing.

The driver code is as follows:

1. gsio_regs[spi->port].interface->data = data;  --> The data is being fetch to the GSIO register

2. gsio_regs[spi->port].interface->ctrl |= GSIO_SB_BUSY;  -->  The GSIO start busy bit will be set (this will cause some delay - I suspect that 414 nano second)

3. gsio_wait_for_xfer_to_complete( spi->port ); --> GSIO will wait for transfer to complete i.e. polling will take place and hence the maximum inter-byte delay takes place

The above is a driver code which is been written as per the hardware algorithm and hence I said we cannot do much about it.

I hope this solves your doubt related to inter-byte delay.

Regarding the slew rate: I need to ask the internal team and will get back to you on this once I have a proper explanation about it.

Thanks and regards

View solution in original post

New Contributor

Hello,

Thank you for your descriptive answer and for contacting the internal team. I am waiting for the updates from their side about slew rate.

Best,

Sergei

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