- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I am using WICED-Studio-6.0 on CYW943907AEVAL1F platform.
I am facing a trouble of CYW43907 SPI behavior.
When I write "0x01" to SPI device, the device can't get the data correctly.
Please see the oscilloscope waveform below. somehow the last bit width is half of clock period.
This is a reason why SPI device can't get the data.
Please let me know how I can fix it.
Solved! Go to Solution.
- Labels:
-
SPI
- Tags:
- spi
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Morise,
This is an internal issue with the gsio driver. The last bit width will only last for half the clock period. Could you change the driver to bit banging and see if this issue persist. Go though the following blog to see how to change the driver. SPI in CYW43907
-Thanks
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Morise,
This is an internal issue with the gsio driver. The last bit width will only last for half the clock period. Could you change the driver to bit banging and see if this issue persist. Go though the following blog to see how to change the driver. SPI in CYW43907
-Thanks
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for the answer.
BTW, is spi_bb_driver only for SPI_0 ?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yes, spi_bb_driver is only for SPI_0.
-Thanks
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for your quick response.
If I want to use SPI1, I can use spi_gsio_driver only. But this driver causes
the last bit half period problem. Which means we can't use SPI1 at all ?
Or are there any way to use SPI1 ?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Could you give the hold time and setup time details of the slave that you are using.
The last bit lasting for half a clock cycle won't be an issue as long as there is no setup and hold time violation. Using a clock beyond 10Mhz could prevent the last bit from latching at the slave side.
For example, for 10Mhz , the half clock period is 50ns. For a slave that has a setup and hold time of 25ns, it would be unwise to use a frequency higher than 10Mhz since it barely satisfies the minimum time constraints.
So if you are using the spi_0/spi_1 interface, you have to limit the frequency to 10MHz(max).Best is to use 5Mhz or less.
What is the clk that you are expecting to achieve in your design.
-Thanks,
Vinayak
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thank you for detail explanation.
I understood how to use it.