CYW43907 J-Link Communication Error

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OlKa_3358896
Level 4
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Hi. We have custom board with CYW43907 chip. Communication error had occurred when we tried connect to device with J-Link: "Error: Cortex-A/R (connect): Communication error when trying to read IDR of AP[0]."

Please help with this issue.

CYW_Jtag_Err1.png

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1 Solution

hello:

Do you have chance to change VDDIO to 3.3v for a try ?  if 3.3V is ok, we can focus the debug to the voltage setting with J-link. 

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Zhengbao_Zhang
Moderator
Moderator
Moderator
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hello:

     If you are using Jlink Segger, please check this thread for the connection and configuration.

Downloading and debugging CYW43907 using Jlink Segger

then check the possible reason of failure from this link.

J-Link cannot connect to the CPU - SEGGER - Support Wiki

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Hi. Thanks. But it is not problem with J-Link. It works fine with CYW943907AEVAL1F board.

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hello:

Do you mean your J-link+ CYW943907AEVAL1F works fine.

but your J-link + your 43907 board has communication errors.

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Yes.

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Hello:

  if so, I think your environment should be no problem,   kindly check the hardware connections by comparing with our EVB system, thanks.

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We have similar design with EVB, except VDDIO and VDDIO_SD is 1.8 V.

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hello:

Do you have chance to change VDDIO to 3.3v for a try ?  if 3.3V is ok, we can focus the debug to the voltage setting with J-link. 

OlKa_3358896
Level 4
Level 4
First like received First like given

Problem resolved with new board revision. Thanks to all)