WICED CYW20719-B1: How to reduce the GPIO output current leak

[LixinD_46]

Hi Team,

After configured a GPIO pin (such as P13) as "GPIO_INPUT_ENABLE | GPIO_OUTPUT_ENABLE" and the default value set to "GPIO_PIN_OUTPUT_HIGH",

then another MCU tried to control the configured GPIO and put it down to the ground as an input to the CYW20719-B1, we can find that the current leak is ~21.5mA.

It's too high.

So, without adding any external resistors, is there any method to reduce the current leak by configuring in the FW internally, just as the PSoC do (such as configured as internal pull up output)?

And one more question, are there pull up and pull down internal resistors for all GPIO? if so, what is the exact value of these internal pull up and pull down resistors?

Thanks,

Dudley

[Anonymous]

You cannot set the pin as OUTPUT_ENABLE and drive the pin from another MCU. That is going to destroy the chip!

[LixinD_46]

If just set the pin as "GPIO_INPUT_ENABLE", the result is same, the current is too high.

And I think, the pin should be able to be configured as "GPIO_INPUT_ENABLE | GPIO_OUTPUT_ENABLE" for both input and output, it's a normal usage.

Thanks,

Dudley

[WinstonF_61 · Accepted solution]

Yes there are Pull Up & Pull Down resistors, that can be activated using the 'GPIO_PULL_UP' or  'GPIO_PULL_DOWN' macros while configuring the GPIO Pin. For E.g. The below statement will configure the port P30 as an Input pin with a Pull Up enabled.

wiced_hal_gpio_configure_pin( WICED_P30, GPIO_INPUT_ENABLE | GPIO_PULL_UP , GPIO_PIN_OUTPUT_HIGH);

Also having 2 Strong Drive GPIO's connected to each other is not a good idea for both devices. Having the Pull up is the correct method.