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WICED Studio Bluetooth

New Contributor

Hi,

I'm using the CYW920735 EVB-01. I've altered the DIP switches for SW9 to off position so that I can use the DEBUG header J13. Using Jlink command line I can connect to the USB Jlink device as this correctly reports the ID, but I can't connect to the CYW20735 via SWDIO and SWDCK as a plain vanilla Cortex M4? I've reset the board in case any firmware I've tried disables the P2/P3 pins and I have tried the SW9 DIPS in the on position. Nothing works! The CYW20735 definitely includes a debug interface so what am I missing? Is the only way to program the device via BT_UART? Please help!

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1 Solution
Moderator
Moderator

Hi,

I connected to the CYW20735 using the JLink Command Line by using the J13 Debug Header via The ARM-JTAG 20-10 pin adapter.

The configurations to be done in the WICED SuperMux GPIO Pin configuration are as follows:

1. Remove the WICED_P02 and WICED_P03 pins which are configured as GPIO's
2. Add the SWD functionality and add WICED_P02 as ck pin and  WICED_P03 as io pin

Add the line : 'C_FLAGS += -DDEBUG' in the makefile

Modify the make target to path-CYW920735Q60EVB_01 download DEBUG=1

Program the device and you should be able to connect using the JLink Command Line.

View solution in original post

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8 Replies
Moderator
Moderator

Hi,

This thread on CYW20719 dealing with JLink may be helpful Cypress CYW920719Q40-B1 eval kit debugging

Also you could refer to this user kit guide to help you out https://www.cypress.com/file/428486/download

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New Contributor

Hi,

thanks for info provided.

The first link looks interesting and I'm sure will prove useful.

My problem is the GDB Server can't connect to the target. It's as if the debug interface is disabled or I've got the wrong pins / mixed up.

I have triple checked everything and sure of pins. I'm familiar with embedded systems and debuggers etc but the lack of concrete information is frustrating. Looking at the CYW20735 datasheet what is the purpose of pin 17 JTAG_SEL the datasheet say's this should be grounded for applications. I have made my own PCB and have tried this pin at GND and VDD and tried connecting. This still fails.

I guess the boot ROM checks this pin and if pulled high enables P2 and P3 as SWD pins otherwise GPIO?

Please any more help / suggestions?

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Moderator
Moderator

Hi,

I connected to the CYW20735 using the JLink Command Line by using the J13 Debug Header via The ARM-JTAG 20-10 pin adapter.

The configurations to be done in the WICED SuperMux GPIO Pin configuration are as follows:

1. Remove the WICED_P02 and WICED_P03 pins which are configured as GPIO's
2. Add the SWD functionality and add WICED_P02 as ck pin and  WICED_P03 as io pin

Add the line : 'C_FLAGS += -DDEBUG' in the makefile

Modify the make target to path-CYW920735Q60EVB_01 download DEBUG=1

Program the device and you should be able to connect using the JLink Command Line.

View solution in original post

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New Contributor

Hi,

thanks for your continued help.

So to be clear I have to program a device with a firmware first that enables the SWD pins (P02, P03).

On my prototype PCB I don't have the BT uart available as I was going to do everything over SWD as I have done on many other designs and parts. So this PCB is useless since I would have to flash a SWD aware firmware before I could use the SWD interface for programming!

What is the purpose of the JTAG_SEL (pin 17)?

Regards.

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Moderator
Moderator

Hi,

The JTAG_SEL pin is used to enable the JTAG Debugging feature.

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New Contributor

Hi,

I hoped so. Holding this pin to VDD still doesn't change anything and the CY20735 can't be connected to using SWD. Are there any reference manuals that provide detailed information on this? Is there anything else I can try. Or am I stuck with BT UART for the initial firmware programming?

Thanks.

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Moderator
Moderator

Hi,

There are no reference manuals regarding connection of SWD to CYW20735 available.

The initial firmware programming has to be through the BT UART.

Thanks

New Contributor

Hi,

thanks again. So the JTAG_SEL pin doesn't really do anything and is a bit of a red herring! If it's functionality matched it's label you would expect the ROM to enable SWD pins when this was pulled high. So a new part could be debugged even without any firmware or even without a serial flash.

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