CYW20706 SPI flash SS section erased abnormally .

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towa_2281366
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5 sign-ins First solution authored First reply posted

Hi, we are using CYW20706+Wiced6.4 for an important project,  after days of pressure test, we found a tricky problem:

In a fast booting senario (power on/off hundreds times ), part of SS section  (2~3KBytes from address 0x0000) might be written to 0 , so the chip will boot to HCI mode as it think the SPI flash is invalid, although the application area (start from 0x4000) is still there.

This is a huge risk for us  as when  SS corrupted , the chip can not work at all !

Can anyone help me ?

HELP!

THANKS!

 

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1 Solution

For the abnomal chip,  i notice that it boot to HCI mode (send hci reset command 01 03 0C 00 to chip , chip response 04 0e 01 03 0c 00 ), so i  remove the SPI flash and attach to an exteral MCU (i.e. STM32F4) for content reading, and it turn out that the SS flash area corrupted. 

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3 Replies
SheetalJ
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First comment on KBA 750 replies posted 500 likes received

Hi @towa_2281366 ,

Static Section of the external flash is used internally by the chip FW. How do you notice that 0 is getting written to SS? Are you seeing any change in application behavior afterwards?

 

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For the abnomal chip,  i notice that it boot to HCI mode (send hci reset command 01 03 0C 00 to chip , chip response 04 0e 01 03 0c 00 ), so i  remove the SPI flash and attach to an exteral MCU (i.e. STM32F4) for content reading, and it turn out that the SS flash area corrupted. 

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towa_2281366
Level 1
Level 1
5 sign-ins First solution authored First reply posted

Add some more details:

1. In nomal circumstance, the chip works fine, i.e. Using an external MCU's gpio to control a LDO for powering on/off 20706 periodic, after test 100000 times , chip boot normal.

2. Disaster happens in a "fast booting" senario,  powe jitter may exist in the end product when booting, i doubt that the boot loader of chip may  have write actions to SS area.

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