SPI on BCM920732TAG

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Anonymous
Not applicable

I'm using the BCM920732TAG board with the 1.1.0 WICED Smart SDK. I'm trying to get SPI slave mode working, but I'm having pretty major issues since many of the API functions are either not documented, or have their documentation limited to just the bare function prototype itself. (Was the Doxygen generated API documentation ever actually finished?)

Specific question:

The spi_comm_slave app example uses the following code to enable interrupt on the flow control pin:

interrupt_handler_mask[SPIFFY2_INPUT_FLOW_CTRL_PORT] |= (1 << SPIFFY2_INPUT_FLOW_CTRL_PIN);

// Now register the interrupt handler.

gpio_registerForInterrupt(interrupt_handler_mask, application_gpio_interrupt_handler, NULL);

In my code, I would like to clear the Rx FIFO at the beginning of chip select, then read stuff out at the end of chip select. I think I'm only getting the interrupts at the beginning of chip select at the moment. How can I enable interrupts for both edges on chip select? The gpio_registerForInterrupt() function is completely undocumented, and it seems like a rather critical API function.

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1 Solution

Within the SDK, please refer to the /WICED-Smart-SDK/Apps/spi_comm_master and /WICED-Smart-SDK/Apps/spi_comm_slave examples as these are tested and have been designed to work with one another.

View solution in original post

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5 Replies
Anonymous
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I thought of a few more questions on that topic-

* If the CS triggers interrupts on both edges, will I get two separate invocations of my handler even if those two interrupts are really close together? (eg, 10 uS)

* What sort of delay should I expect to see between the interrupt occurring and my handler getting invoked?

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Anonymous
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I've simplified the problem down a bit. My master device is transmitting the sequence 0xAB 0xFF 0xFF once per second with a 100 KHz clock to the BCM20732. I can see SPI bytes coming through, but I usually only see the last byte. Occasionally, I see all three bytes. A logic trace of the SPI bus is attached to this post. The following ports are used:

P4 - MOSI

P3 - SCLK

P2 - CS

P25 - MISO

I observe the following in my debug console:

cs[1]

RxFifoCount[1]

Dumped[FF]

cs[1]

RxFifoCount[3]

Dumped[AB]

Dumped[FF]

Dumped[FF]

cs[1]

RxFifoCount[1]

Dumped[FF]

cs[1]

RxFifoCount[1]

Dumped[FF]

cs[1]

RxFifoCount[1]

Dumped[FF]

cs[1]

RxFifoCount[1]

Dumped[FF]

Questions:

* Why do I only receive the last byte most of the time?

* The spi_comm_slave example has the CS pin trigger interrupts on both edges, but when running that example code, I only get one interrupt per packet. Does that example actually work?

* When will the documentation be finished?

* Can I strip all of the bluetooth code out of an application so I can run just the SPI stuff? If so, how?

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Anonymous
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Hello gfreese,

Are you still struggling with the SPI code?

Please let us know.

Thanks,

JT

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Anonymous
Not applicable

Hi JT,

I want to know that the spi pin assignment of gfreese:

P4 - MOSI

P3 - SCLK

P2 - CS

P25 - MISO

Is it reasonable and available for spi master and slave com application?

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Within the SDK, please refer to the /WICED-Smart-SDK/Apps/spi_comm_master and /WICED-Smart-SDK/Apps/spi_comm_slave examples as these are tested and have been designed to work with one another.

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