I am in the process of adding the following ESD section to the datasheets of the BCM2732/36/37 SoCs (thanks again to nsankar for helping me pull this together):
ESD Test Models
ESD can have serious detrimental effects on all semiconductor ICs and the system that contains them.
Standards are developed to enhance the quality and reliability of ICs by ensuring all devices employed have
undergone proper ESD design and testing, thereby minimizing the detrimental effects of ESD. Three major test
methods are widely used in the industry today to describe uniform methods for assessing ESD immunity at
Component level, Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). The
following standards were used to test this device:
Human-Body Model (HBM) – ANSI/ESDA/JEDEC JS-001-2012
The HBM has been developed to simulate the action of a human body discharging an accumulated static charge
through a device to ground, and employs a series RC network consisting of a 100 pF capacitor and a 1500Ω
(Ohm) resistor. Both positive and negative polarities are used for this test. Although, a 100 ms delay is allowable
per specification, the minimum delay used for testing was set to 300 ms between each pulse.
Machine Model (MM) – JEDEC JESD22-A115C
The MM has been developed to simulate the rapid discharge from a charged conductive object, such as a
metallic tool or fixture. The most common application would be rapid discharge from charged board assembly
or the charged cables of automated testers. This model consists of a 200 pF capacitor discharged directly into
a component with no series resistor (0Ω). One positive and one negative polarity pulses are applied. The
minimum delay between pulses is 500 ms.
Charged-Device Model (CDM) - JEDEC JESD22-C101E
CDM simulates charging/discharging events that occur in production equipment and processes. The potential
for a CDM ESD events occurs when there is metal-to-metal contact in manufacturing. CDM addresses the
possibility that a charge may reside on the lead frame or package (e.g., from shipping) and discharge through
a pin that subsequently is grounded, causing damage to sensitive devices in the path. Discharge current is
limited only by the parasitic impedance and capacitance of the device. CDM testing consists of charging
package to a specified voltage, then discharging the voltage through relevant package leads. One positive and
one negative polarity pulse is applied. The minimum delay between pulses is 200 ms.
Results Summary
- ESD Test Voltage Level Results:
- HBM +/– 2KV PASS
- MM +/– 150V PASS
- CDM +/– 500V PASS
These should be published to the site within the next few days by gewing
david_armour
