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WICED Smart Bluetooth

Anonymous
Not applicable

I have read through the Hardware Interfaces document, but some things are still not clear.

Are there any restrictions around using the various interfaces at the same time?  For example, if we are using the PUART to communicate with our main system processor, is the functionality limitted at all while the module is using I2C to comm with external EEPROM?

Thanks

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ArvindS_76
Employee

PUART and I2C don't have any dependency. You can use both at the same time. SPI2 and PUART however do have some restrictions, see the datasheet or the HW interfaces document (in short - PUART RX and SI2 have to be on the same GPO bank). I2C and SPI1 share GPIOs. With SDK 2.1 and above, there is an optional patch with which you can use I2C when SPI1 is used for NV storage (serial flash). But the other way where you want to use SPI1 as an SPI master when using I2C EPROM slave is not possible.

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8 Replies
ArvindS_76
Employee

PUART and I2C don't have any dependency. You can use both at the same time. SPI2 and PUART however do have some restrictions, see the datasheet or the HW interfaces document (in short - PUART RX and SI2 have to be on the same GPO bank). I2C and SPI1 share GPIOs. With SDK 2.1 and above, there is an optional patch with which you can use I2C when SPI1 is used for NV storage (serial flash). But the other way where you want to use SPI1 as an SPI master when using I2C EPROM slave is not possible.

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MichaelF_56
Moderator
Moderator

"With SDK 2.1 and above, there is an optional patch with which you can use I2C when SPI1 is used for NV storage (serial flash). But the other way where you want to use SPI1 as an SPI master when using I2C EPROM slave is not possible."

Note that this applies to the SOC, not the module.  On the module, I2C is fixed and connected to the onboard EEPROM.

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Anonymous
Not applicable

Hi, Arvinds,

Where can i find this optional patch?

thanks.

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MichaelF_56
Moderator
Moderator

The patch is for the SOC, not module. It also requires factory support to get working, so CSP may be a better path.

Are you using a BCM2073X SOC in the design? On the module, I2C is fixed and connected to the onboard EEPROM.

arvinds

j.t

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Anonymous
Not applicable

yes, I'm using BCM20737 SOC (BCM920737TAG board).

I had thought the patch might be hidden somewhere in the WICED 2.1.1.

So, if i only test with 20737TAG board in lab without the factory support, i can not install the patch, right?

thanks.

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ArvindS_76
Employee

The patch is called enable_spiffy1_i2c_interop.a. Add this to your application's makefile.mk:

APP_PATCHES_AND_LIBS += enable_spiffy1_i2c_interop.a

Then clean and rebuild your app before downloading. When accessing the I2C slave when using SPI serial flash, use the API in i2cm.h instead of cfa_*() API (if you use I2C EEPROM for NV, you must always use cfa_* API because there is a known issue with i2cm.h API that will be fixed in a future SDK release).

If you are using the tag board, ensure that you follow the instructions in WICED™ Development System (Hardware User's Manual) to switch to using SF instead of I2C EEPROM.

Anonymous
Not applicable

Found it at \\Wiced-Smart\tier2\brcm\libraries\lib\20736\

thanks a lot for your quick response ^_^

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Anonymous
Not applicable

hi, Arvinds,

You said that "in short - PUART RX and SI2 have to be on the same GPO bank."

Here I consider "SI2" as MOSI of SPI2, right?

But according to MMP920732HW-AN101-R_WICED Smart Hardware Interfaces.pdf, page 14:

If a peripheral UART is also being used by the application, the SPIFFY2 signals and peripheral UART RX

signal must be on the lower pad bank (P0 through P7) or on the upper pad bank (P24 through P39). Thus,

SPIFFY1 or SPIFFY2, and peripheral UART RX, cannot be on two different pad banks.

Here i consider "SPIFFY2 signals" as all four signal lines (cs, miso, mosi and clk).

So, which statement is more accurate?

thanks.