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* What is the maximum SPI frequency for SPIFFY2? The documentation is conflicting.
20732-DS107-R pg 35 specifies:
"12 MHz when: VDDIO >= 2.2v
6 MHz when: 2.2V > VDDIO >= 1.62v"
920732HW-AN100-R pg 7 specifies:
"The maximum SCLK speed supported by SPIFFY2 is 6 MHz at all IO supply voltages."
* Are the maximum frequencies different for master and slave mode?
* Is there a minimum SPI frequency?
* For a given SPI transmission size, will the device consume more energy with a high clock rate (6 MHz), or a low clock rate (100 KHz)
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While SPIFFY1 (SPI 1) can run at 12MHz, it shares the SCL+SDA with the I2C interface, which is connected internally to the 512K of EEROM inside the module.
SPIFFY2 (SPI 2) can be configured as either master or slave and supports a max speed of 6 MHz.
Both SPI interfaces support all four SPI modes and either endianness.
I'm not aware of a min clock rate on SPIFFY2.