USB

Hi,

I worked through the UVC example and got video streaming working.  I then worked through the GpifToUsb example and got data read out working.  Now I am trying to merge them and continuously read out data from an ADC without dropping data.  To do this, I began with the GpifToUsb example and added a simple GPIF project with two threads (0,1):

Next, I added a MANY_TO_ONE auto DMA channel to GpifToUsb:

    //try creating a many to one dma channel
    CyU3PDmaMultiChannelConfig_t dmaMultiConfig;
    CyU3PMemSet ((uint8_t *)&dmaCfg, 0, sizeof (dmaMultiConfig));
    dmaMultiConfig.size           = CY_FX_DMA_BUF_SIZE;
      dmaMultiConfig.count          = CY_FX_DMA_BUF_COUNT;
      dmaMultiConfig.validSckCount  = 2;
      dmaMultiConfig.prodSckId [0]  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_0;
      dmaMultiConfig.prodSckId [1]  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_1;
      dmaMultiConfig.consSckId [0]  = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0);
      dmaMultiConfig.prodAvailCount = 0;
      dmaMultiConfig.prodHeader     = 0;                 /* 12 byte UVC header to be added. */
      dmaMultiConfig.prodFooter     = 0;                  /* 4 byte footer to compensate for the 12 byte header. */
      dmaMultiConfig.consHeader     = 0;
      dmaMultiConfig.dmaMode        = CY_U3P_DMA_MODE_BYTE;
      dmaMultiConfig.cb 			= NULL;
      dmaMultiConfig.notification   = 0;
      //dmaMultiConfig.notification   = CY_U3P_DMA_CB_CONS_SUSP; // CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;
      //dmaMultiConfig.cb             = GpifToUsbDmaCallbackMulti;
     
      	  apiRetStatus = CyU3PDmaMultiChannelCreate (&glDmaChHandleMulti, CY_U3P_DMA_TYPE_AUTO_MANY_TO_ONE,
              &dmaMultiConfig);
      if (apiRetStatus != CY_U3P_SUCCESS)
      {
          /* Error handling */
          CyU3PDebugPrint (4, "DMA Channel Creation Failed, Error Code = %d\n", apiRetStatus);
          CyFxAppErrorHandler (apiRetStatus);
      }

The result is:

USB event: 11 0
About to connect to USB host
USB event: 0 1
CY_U3P_USB_EVENT_CONNECT detected
CyFxApplnInit complete
USB event: 8 0
USB event: 5 1
setting up dma
              DMA Channel Creation Failed, Error Code = 64

Any idea what I'm doing wrong?  

Hello, I am currently developing a USB PD power bank that utilizes bi-directional 60W input and 100W output. My plan is to use SC8815 I2C bidirectional buck-boost controller for Power and CYPD 3171 as the PD controller. I want to use CYPD3171 to control SC8815 over I2C to configure SC8815 modes(input and output) as well as output and charging voltage, etc. I also want CYPD3175 to inform the main MCU of PD modes, voltages, currents etc. My question is that what is the best way to achieve this functionality? Should I use EZ-PD config utility or PSOC programmer to write the code? Also, how should I upload the program onto CYPD3175, can I use an ST-Link, or use another MCU over I2C? Can someone recommend me a software and programmer combo? I saw this reference design using sc8915 which is extremely similar to my application, and I think I am going to reference the schematic, but I don't see where the code is located, could someone also inform me of where it is located so I can use it as a reference if possible? I am new to the CCG3 ecosystem, thank you very much!

Hi everyone,

I want to configure the DS-1 port of CY611 EZ-USB HX3PD EVK to supply 12V. But when I try to configure  using EZ-USB HX3PD configuration Utility - PD Controller- Port 1, it shows me error - Atleast one 5V PDO should be enabled in Source PDO. But if add another source PDO of 5V, it does not save the configuration.

Can anyone help please ?

Thanks

Sugreev

I need to achieve low standby power consumption in a system with an FX3 and a Xilinx FPGA.  This system primarily remains in a low power idle state for 99% of the time where neither the FX3 or FPGA is being used. 

Referring to the block diagram below, the PSoC is powered continuously through the LDO.  The PSoC controls switching regulators that power a USB host, the FX3 and the Xilinx.  The PSoC also performs aggressive power management to maximize battery life.

The PSoC turns on power to the FX3 and the Xilinx FPGA.  All of the FX3's core VDD(x) and IO VIO(x) supplies are powered.  The FPGA's IO banks connected to the FX3 are powered as well to avoid the FX3 driving an unpowered FPGA or vice versa.

Later, the PSoC will apply power to the USB Host system which in turn powers VBUS on the USB connector.  VBUS is used to hold the FX3 in RESET (using an RC network) until VBUS is stable.

Questions:

1. Will this method of powering the FX3 work? 

2.  I'm confused about the use of VBATT versus VBUS FX3 signals.    The Super Speed Explorer connects VBUS on the USB connector to the FX3's VBUS signal.  The FX3's VBAT signal is not connected on the SSE.   The FX3 DVK connects a select-able power supply(+5V,+3.3,+2.5) voltage or a battery through a diode OR to the FX3's VBAT signal.  VBUS from the USB connector is connected to the FX3's VBUS signal.    Other FX3 based boards connect the VBUS line from the USB connector to both VBAT and VBUS on the FX3.  I'm not sure what is the correct usage for my application.  Please explain.

3. I have other H/S USB devices that would share one USB Gen 3 connector.  It is possible to insert a CY7C65642 USB hub on the D+ and D- signals?

Thanks for your help!

Wayne

3.

Dear community,

I'm trying to use a GPIO pin that was previously used as a PWM.
The problem is that when I re-configure it, it stay in 3-state mode instead of High level. 

What I'm doing wrong?

In attached you can find the code, many thanks in advance.

Regards,
Corrado

This is a continuation of this thread.

I am considering replacing the Renesas USB host controller with FX3.

The device has two signals: "VBOUT" (external power output enabled) and "OVCUR0" (overcurrent detection).

I want FX3 to have a similar function. Can it be implemented in FX3? Especially, I think that overcurrent detection requires a fast response using as interrupts.

Thanks,
Tetsuo

Hello

"AN65974.zip"-> "FX3 Firmware"-> "Slave Fifo Sync"

→ There is the following description on line 892 of "cyfx slfifosync"

io_cfg.gpioSimpleEn [0] = 0;
io_cfg.gpioSimpleEn [1] = 0x08000000; / * GPIO 59 * /
io_cfg.gpioComplexEn [0] = 0;
io_cfg.gpioComplexEn [1] = 0;

Q1)
What will happen to the terminal state when all gpioSimpleEn are set to 0 (disabled)?
Q2-1) I think that the GPIO_SIMPLE register setting described on P.590 of FX3 TRM corresponds to the terminal setting in this case. Is this correct? if so,  would like to know the terminal status and necessary terminal processing in that case.
Q2-2) I think that DRIVE_HI_EN: 0 is a tri-state output if the initial value of the register. Is this correct?
Q2-3) Is it okay if external terminal processing is not required in the case of tri-state?

Please answer each  question mentioned above?

Best Regards

Arai

Hello,

I'm curious to know if it should be possible to send an invalid vendor request code to the Default USB device on an FX2[LP]. I know that the request code 0xa0 is always recognized before and after renumeration. I attempted to send another code that is implemented in our firmware to the default USB device and I expected that it would simply reject the request and stall endpoint 0. In our Windows driver when I attempted to send a URB that packages that vendor request, USBD seems to block indefinitely. After seeing that, I put in logic to cancel the IRP after a timeout elapsed. However, when I went to continue through our usual process of downloading firmware, it seems to malfunction, as if it consumed part of my invalid vendor request and cached it before processing the subsequent 0xa0 vendor request.

Is this just something I should completely avoid doing [sending unrecognized vendor request codes to it]? I managed to move on to a different technique but my motivation was to try to discern between our device having renumerated with firmware and a fresh firmware-less enumeration state. Granted, one can use vendor, product, and device ID combinations to deduce this, but this was something of an academic exercise for me and I'm genuinely curious. I could not find anything in the TRM that would tell me what to expect under this scenario.

~Thanks

Hello Infineon Experts,

We use a CX3 and one or two related image sensors on our board, and we are facing a CY_U3P_ERROR_FAILURE value returned by the CyU3PMipicsiSetSensorControl() API. This behavior is random, but the error rate is over 20 %.

We probed the I2C bus and some other significant signals (CX3_RESET*, CX3_XRESET and CX3_XSHUTDOWN), to look what’s happen (see attached pictures):

• On successful execution, a first reading of Register 0x0012 (CY_U3P_MIPICSI_REG_GPIOIN) is done, bits [2:1] of this value are set to ‘1’ to drive High XRESET and XSHUTDOWN pins, the changed value is written to Register 0x0014 (CX3_CSI_SENSOR_SIG_VAL) and a second reading of Register 0x0012 is performed to be sure that Register 0x0014 is correctly written. So, reserved bits of Register 0x0014 are preserved as requested to section 1.10.7 of CX3 TRM.
• On fail execution, the second reading of register 0x0012 doesn’t match the writing to Register 0x0014 and the CyU3PMipicsiSetSensorControl() API returns CY_U3P_ERROR_FAILURE. The difference concerns the reserved bit 0.

Do you have an explanation for this error CY_U3P_ERROR_FAILURE?

For your information, both SDA and SCL signals are pulled high with 2kΩ resistors, and the I2C block is initialized (by calling CyU3PMipicsiInitializeI2c() API) before initializing the MIPI-CSI-2 block (i.e. before calling CyU3PMipicsiInit() API).

Best Regards,

Eric.