Hello,
We have not clearly understood your issue. As per your description, you have not modified the AN65974 state machine. This means that when FLAGC is 1, it indicates that the buffer is not empty and when FLAGC is 0, it indicates that the buffer is empty. I hope you are aware of this.
Now, the DMA buffer size used in the firmware is 16KB and the buffer count is 2. The DMA buffers will be committed to the P Port only when any of the following happens:
1. The DMA buffer is completely filled. This means that the host should send 16KB data.
2. When a short packet is received from the USB host. A short packet is a packet having size less than 1024 bytes. This means that the 10B that you transfer is a short packet and the DMA buffer will be sent to the P Port.
3. When a ZLP is issued by the USB host.
Can you please elaborate the following paragraph so that we can understand the problems better?
There are some solutions when i test my project. When i use control center or my software transfer 1024B from PC to FPGA , 8 times after,the FLAGC will become 1;When i use control center transfer 10B from PC to FPGA,control center will report error code 997 when i transfer third time.the picture2(in the accessory) shows the solution. At the same time,ILA shows the FLAGC will become 1 when i first transfer 10B,and it will be 1 all the time.Because of this, the FPGA state machine will work bad,the sloe and slrd will 1 all the time.
As per picture 2, I understand that you are transferring the 10B of data three times. As 10B is a short packet, the DMA buffers will be filled. So, the first 2 transmission will fill both the DMA buffers. As error 997 is shown in control center, we can conclude that the FPGA is not reading the data correctly.
Also, as per your description, the watermark flag is set to 6. So, based on the following formula:
The number of data words available for reading (while keeping SLOE# asserted) after the clock edge at which
the partial flag is sampled asserted = watermark x (32/bus width) – 1 = 6 - 1 = 5
This means that once the watermark flag is asserted, the number of data words available for reading will be 5. Each data word here is of 32 bits (4 bytes). So, the amount of data that should be read by FPGA after the watermark flag goes low is 20 bytes. This could be a reason for the FPGA to drive SLOE for a longer time than required. Can you please try reducing the watermark value from 6 to 2 and let me know the results?
Best Regards,
Jayakrishna
