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USB Superspeed Peripherals

chji_4822211
New Contributor II

there are two questions.

First, the document AN65974 said:(a) The number of data words available for reading (while keeping SLOE# asserted) after the clock edge at which the partial flag is sampled asserted = watermark x (32/bus width) – 1.But when i run the program which have modified based on the AN65974 routine. I found that SLOE keeping 6 clk,and i am sure that the watermark of flagd is 6.This why? 

Second, I have modified the FM based on AN65974, i only set one endpoint for data from PC to FPGA.  I have modified the verilog code based on AN65974.   When i transfer many Bytes from control center,FPGA work nomally.But when i transfer a few Bytes from control center, there was an error code 997,and Flagd stay on 0. When i use the software designed by myself, the function xferdata will return false.

can you provide some thoughts to locate reason of those 

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1 Solution
JayakrishnaT_76
Moderator
Moderator

Hello,

We have not clearly understood your issue. As per your description, you have not modified the AN65974 state machine. This means that when FLAGC is 1, it indicates that the buffer is not empty and when FLAGC is 0, it indicates that the buffer is empty. I hope you are aware of this.

Now, the DMA buffer size used in the firmware is 16KB and the buffer count is 2. The DMA buffers will be committed to the P Port only when any of the following happens:

1. The DMA buffer is completely filled. This means that the host should send 16KB data.

2. When a short packet is received from the USB host. A short packet is a packet having size less than 1024 bytes. This means that the 10B that you transfer is a short packet and the DMA buffer will be sent to the P Port.

3. When a ZLP is issued by the USB host.

Can you please elaborate the following paragraph so that we can understand the problems better?

There are some solutions when i test my project. When i use control center or my software transfer 1024B from PC to FPGA , 8 times after,the FLAGC will become 1;When i use control center transfer 10B from PC to FPGA,control center will report error code 997 when i transfer third time.the picture2(in the accessory) shows the solution. At the same time,ILA shows the FLAGC will become 1 when i first transfer 10B,and it will be 1 all the time.Because of this, the FPGA state machine will work bad,the sloe and slrd will 1 all the time.

As per picture 2, I understand that you are transferring the 10B of data three times. As 10B is a short packet, the DMA buffers will be filled. So, the first 2 transmission will fill both the DMA buffers. As error 997 is shown in control center, we can conclude that the FPGA is not reading the data correctly.

Also, as per your description, the watermark flag is set to 6. So, based on the following formula:

The number of data words available for reading (while keeping SLOE# asserted) after the clock edge at which
the partial flag is sampled asserted = watermark x (32/bus width) – 1 = 6  - 1 = 5

This means that once the watermark flag is asserted, the number of data words available for reading will be 5. Each data word here is of 32 bits (4 bytes). So, the amount of data that should be read by FPGA after the watermark flag goes low is 20 bytes. This could be a reason for the FPGA to drive SLOE for a longer time than required. Can you please try reducing the watermark value from 6 to 2 and let me know the results?

Best Regards,
Jayakrishna

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12 Replies
JayakrishnaT_76
Moderator
Moderator

Hello,

Please let us know the following so that we can understand the problems better:

1. What are the changes made on the default AN65974 project? Are there any modifications done on the GPIF II state machine?

2. What is the bus width used?

3. What is the size of data transferred to the OUT endpoint in the second question? It seems like the FPGA is not reading the data properly from FX3. This could be the reason for the control center to report error code 997.

Best Regards,
Jayakrishna
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chji_4822211
New Contributor II

Hello,

Thanks for your reply.

My project's bus width is 32bit.The changes as follows: GPIF II state no change.Firmware : what i have modified is i only use one bulk endpoints 0x01,delete other endpoint 0x81.  FPGA verilog: I only use the Stream_OUT state machine and delete others.   

There are some solutions when i test my project. When i use control center or my software transfer 1024B from PC to FPGA , 8 times after,the FLAGC will become 1;When i use control center transfer 10B from PC to FPGA,control center will report error code 997 when i transfer third time.the picture2(in the accessory) shows the solution. At the same time,ILA shows the FLAGC will become 1 when i first transfer 10B,and it will be 1 all the time.Because of this, the FPGA state machine will work bad,the sloe and slrd will 1 all the time.

I agree with you. It seems like the first question that i mentioned in last post causes the second question. The picture1(in the accessory) shows the times of my project.The signals named fx_xxx are directly connected with the fx3 hardware. plz help me analyze this time chart ,thanks a lot. 

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chji_4822211
New Contributor II
 
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chji_4822211
New Contributor II

And in the firmware i  set the buffer size is 16KB,the buffer count is 2,burst len is 16.

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JayakrishnaT_76
Moderator
Moderator

Hello,

We have not clearly understood your issue. As per your description, you have not modified the AN65974 state machine. This means that when FLAGC is 1, it indicates that the buffer is not empty and when FLAGC is 0, it indicates that the buffer is empty. I hope you are aware of this.

Now, the DMA buffer size used in the firmware is 16KB and the buffer count is 2. The DMA buffers will be committed to the P Port only when any of the following happens:

1. The DMA buffer is completely filled. This means that the host should send 16KB data.

2. When a short packet is received from the USB host. A short packet is a packet having size less than 1024 bytes. This means that the 10B that you transfer is a short packet and the DMA buffer will be sent to the P Port.

3. When a ZLP is issued by the USB host.

Can you please elaborate the following paragraph so that we can understand the problems better?

There are some solutions when i test my project. When i use control center or my software transfer 1024B from PC to FPGA , 8 times after,the FLAGC will become 1;When i use control center transfer 10B from PC to FPGA,control center will report error code 997 when i transfer third time.the picture2(in the accessory) shows the solution. At the same time,ILA shows the FLAGC will become 1 when i first transfer 10B,and it will be 1 all the time.Because of this, the FPGA state machine will work bad,the sloe and slrd will 1 all the time.

As per picture 2, I understand that you are transferring the 10B of data three times. As 10B is a short packet, the DMA buffers will be filled. So, the first 2 transmission will fill both the DMA buffers. As error 997 is shown in control center, we can conclude that the FPGA is not reading the data correctly.

Also, as per your description, the watermark flag is set to 6. So, based on the following formula:

The number of data words available for reading (while keeping SLOE# asserted) after the clock edge at which
the partial flag is sampled asserted = watermark x (32/bus width) – 1 = 6  - 1 = 5

This means that once the watermark flag is asserted, the number of data words available for reading will be 5. Each data word here is of 32 bits (4 bytes). So, the amount of data that should be read by FPGA after the watermark flag goes low is 20 bytes. This could be a reason for the FPGA to drive SLOE for a longer time than required. Can you please try reducing the watermark value from 6 to 2 and let me know the results?

Best Regards,
Jayakrishna

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chji_4822211
New Contributor II

Hello,

I am so sry for my blurry description,and i am so appreciate for your patience.

And  i have understood the reason for my issue .And i want verify something as follows:

1.FLAGC will be 1 when buffer is not-empty no matter how much Bytes are filled in the buffer?

What i noticed is FLAGC will turn into 1 after host software invoke xferdata function 8 times,that means host transfer 8KB to FPGA.(The size of cmdBuffer is 1024B,len=1024)This why?

tsmit_Endpt->XferData(cmdBuffer, len);

2.As we all know, AN65974 provides FPGA code.According to this code,when i choose the mode is Stream_OUT,it will keeping SLOE# asserted for 6 clocks when the partial flag is sampled asserted.Is that correct?

3.The number of data words available for reading is count by SLOE,not by SLRD?

4.I program host software by CyAPI,i want to know how to transfer short package? And how to transfer ZLP? When i transfer 10B form host to FPGA, i use xferdata function as follow:

tsmit_Endpt->XferData(imgBuffer, len);

The size of imgBuffer is 10B,and len = 10. Is that correct?

 

 

 

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JayakrishnaT_76
Moderator
Moderator

Hello,

Please find my comments for your questions below:

1. Yes, FLAGC will be 1 when buffer is not-empty no matter how much Bytes are filled in the buffer. As you are seeing FLAGC1 when 8KB of data is sent to the device, we feel that the DMA buffer size used is 8KB and not 16KB. The data will be committed to the P Port only if either of the conditions mentioned in my previous response is fulfilled. Here, I think that the buffer itself is getting full. Therefore, the size of DMA buffer used should be 8KB. Can you please share the snapshot of the code that is related to the creation of DMA channel for the U to P port?

2. Yes, this is correct.

3. The number of data words available for reading after partial flag goes from high to low is calculated by the formula shared in my previous response. The AN65974 state machine requires the control signals SLOE and SLRD from the FPGA for driving the data. For this, the FPGA should keep SLOE asserted for the number of data words left to read when the watermark flag goes low. As there is a 2 cycle latency from SLRD to data, the number of clock cycles for which SLRD should be asserted by the FPGA will be the number of clock cycles for which SLOE is asserted - 2. The same is mentioned in AN65974 (snapshot attached below):

JayakrishnaT_76_0-1615881077383.png

These timings should be followed for proper operation.

4. Yes, the usage of xferdata for transmitting short packet is correct.

Best Regards,
Jayakrishna
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chji_4822211
New Contributor II

Hello,

Thanks a lot.I have got 2-4.

Q0: As per your description ,in other words,the FLAGC goes 1 from 0 when the DMA buffers are committed to the P Port? right?

Q1:You are right.I set the buffer size as follow:

                               dmaCfg.size = DMA_BUF_SIZE*size;

                              #define DMA_BUF_SIZE    (16)

When i replace "size" by "1024",the result is my expected as your description.So it is the function named CyU3PUsbGetSpeed() returns CY_U3P_HIGH_SPEED,and causes size = 512.This why?I hope it returns CY_U3P_SUPER_SPEED. I want to know why the function returns CY_U3P_HIGH_SPEED,what should i do? Is that related with hardware physical connection? And how to detected the current usb speed mode ? 

Q2:

I have checked GPIF II State Machine again.IDLE will turn into READ when "SLWR&!SLCS&PKEND&!SLRD&!SLOE".In the FPGA project,when "SLWR&!SLCS&PKEND&!SLRD&!SLOE",

the data bus fx3_data appear 32bits zero.(show in picture1 in my attach).Is that related with the first question? 

 

 

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JayakrishnaT_76
Moderator
Moderator

Hello, 

Please find my comments for your questions below:

Q0: The Flag C will undergo a transition from 1 to 0 only when the DMA buffer becomes empty. This happens only when the FPGA read the data completely from the DMA buffer associated with a P Port socket.

Q1: The API CyU3PUsbGetSpeed() is used for obtaining the operating speed of usb connection at any point of time. If this API returns CY_U3P_HIGH_SPEED, then it means that the device is operating in USB 2.0 mode. This can be due to hardware or firmware issue. Please refer to question 3 of the following API to understand the possible causes and fix for this issue:

https://community.cypress.com/t5/Knowledge-Base-Articles/Trouble-Shooting-Guide-for-the-FX3-FX3S-CX3...

Q2: Please refer to Figure 3 - Synchronous Slave FIFO Read Sequence of AN65974 to understand the Slave FIFO Read sequence. As per the figure, there is a 2 cycle latency between SLRD and data. So, once SLRD is asserted by FPGA, the data will be driven after 2 clock cycles. As per the timing diagram shared in your previous response, the first data driven by FX3 is 0x00000000. This is not related to the first question.

Best Regards,
Jayakrishna
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chji_4822211
New Contributor II

Hello,

Thanks for your reply.

Thanks a lot.I have verified that this FM works in USB3.0 on other board.We are checking our hardware design by our hardware engineer. What is the difference between the USB2.0 and USB 3.0 for FPGA For Read Sequence?

What puzzles me is that when did it happen Flag C  undergos a transition from 0 to 1 ?When i set bufffer size = 16KB,count=2,what i observed is that  transfer 1024B  from host to FPGA ,the FlagC stayed 0.After doing  this transfer 16 times,there was a transition of FlagC from 0 to 1.  In your previous response,FLAGC will be 1 when buffer is not-empty no matter how much Bytes are filled in the buffer. The result that i have obserbed is normal or not? Is a transition of FlagC from 0 to 1  related to  your statement("The DMA buffers will be committed to the P Port only when any of the following happens" )in your previous response?

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JayakrishnaT_76
Moderator
Moderator

Hello,

What is the difference between the USB2.0 and USB 3.0 for FPGA For Read Sequence?

>> There is no dependency between the FPGA implementation and the USB connection speed. The only thing to take care is that the Read sequence is proper irrespective of the USB connection speed.

Also, the status of flag will change only when the buffer is not empty. The producer socket in this case is the USB socket. A DMA buffer will be received by the USB socket and committed to the P Port only if any of the following cases are satisfied:

1. The buffer is full (16KB is received).

2. Short packet is received from host.

3. ZLP is received from host.

1024B is a full packet, so the USB block will expect more data from the host until the DMA buffer associated with the socket gets full/short packet is received/ZLP is received. This is the reason why you do not see a change in the flag status if just 1024B is transferred.

Best Regards,
Jayakrishna
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