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USB Superspeed Peripherals

Anonymous
Not applicable

大家好:

   

首先介绍下自己的问题。我使用FPGA通过CYUSB3014芯片slave fifo接口发送数据至PC。

   

PC端收到的每帧数据之间的间隔时间太长(即每个fifo的数据),于是我测量了下flagb的

   

信号见附件。可以看出,flagb信号的低电平持续时间为270ms,这个时间太长了,远远满

   

足不了项目需求。

   

我的问题是:

   

1. 何种原因造成flagb低电平持续这么久?(即fifo满标志持续时间)

   

2. 可疑问题定位有哪些?

   

3. 有什么解决方案吗?

   

 

   

祝好

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Anonymous
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Hi,

   

If flag B is stuck at low, it means that the Data has not been read by the Host PC. One common reason why this occurs often could be that FX3 has gone into low power mode.

   

The PC might force FX3 to go to low power mode because of which data in FX3's DMA will be left unread.

   

Can you please call CyU3PUsbLPMDisable () API after the CyU3PConnectState API and check?

   

Regards,

   

-Madhu Sudhan

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Anonymous
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Hi,Thanks for your reply,I will test that this week.

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