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I suggest generate a signal PKTEND time out of the package. The sense of how to assert the signal PKTEND, when the FIFO to transfer to the FX3 is EMPTY and current usb endpoint FIFO is NOT EMPTY, during a preset number of cycles the timer.
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I suggest generate a signal PKTEND time out of the package. The sense of how to assert the signal PKTEND, when the FIFO to transfer to the FX3 is EMPTY and usb endpoint FIFO FX3 is NOT EMPTY, during a preset number of cycles the timer.
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Yes, sure. I implemented for controller FX2. For it there is no limit as to assert the signal PKTEND relative to SLWR. I can not really assert whether or not work that way FX3. The documentation is written in the FX3, the signal PKTEND must be set in sync with the SLWR and the last word of data. Do you both work? I do not have board DVK CYUSB3KIT-001, can not test:( Soon to coming ...
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