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USB Superspeed Peripherals

Anonymous
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Hi Guys,

   

   what max size of slave fifo can I configure to an endpoint? what event triggers the DMA between slave fifo and endpoint( slave fifo full/empty or endpoint buffer full/empty)? how to abort the dma?

   

 Thanks

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Anonymous
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The size variable of CyU3PDmaBuffer_t is 16-bit. This would be the restriction of buffer size.

   

Once a USB packet (entire packet) is received it will be transmitted.

   

Have you looked at CyU3PDmaChannelAbort??

   

Regards,

   

Anand

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Anonymous
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Is the event for transferring data (manual mode) from slave fifo to IN endpoint also triggered in the case of terminating a short packet by asserting PKTEND hardware signal?

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Anonymous
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Anand, Thanks for your reply.

   

 if the slave fifo size is limit by CyU3PDmaBuffer_t, it means the slave fifo physical size can be configured to 64KBytes. if the slave fifo is empty. the external processor can transfer a block data of 64KBytes without any interrupt, is it true?

   

thanks!

   

diagman

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Anonymous
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If I have an automatic DMA channel set between the GPIF and an IN type endpoint, can I have ZLP (zero length packet) produced, if the end of the GPIF transfer is exactly the same size as the packet length on the endpoint?

   

 

   

For example, I have the GPIF acting as consumer.  It gets a 1500 byte transfer before the PKTEND signal is asserted.  Assume the IN endpoint has a 1024 packet size.  I would expect the host to get a 1024 byte packet followed by a 476 byte packet.  Is this correct?

   

 

   

Now what happens if I get 1024 transfer on the GPIF before the PKTEND signal is asserted.  Can I get a ZLP sent after the 1024 byte frame goes to the host?  The old FX2 had a mechanism for inserting ZLPs, if the PKTEND was asserted on a boundary of the USB packet size.

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Anonymous
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I have answered part of the ZLP question I posted above.  The GPIF can generate a ZLP under certain condition.  According to the apnote AN65974, we can generate a ZLP by asserting PKTEND, while not asserting SLWR.

   

 

   

This means the external processor needs to be aware of the USB packet size if it is to generate a ZLP.  Is there a way we can generate a ZLP from the ARM processor?

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Anonymous
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If you delay the PKTEND strobe you do not have to look at the packet size. We are using this mechanism at the FPGA to FX2 connection. 4 IFCLK cycles after the last word of the packet we generate the PKTEND strobe and do not transfer further data in this time. In the case there were a multiple of 512 bytes transferred a ZLP is generated. If the size was smaller then a full packet, the packet is commited without ZLP. This works great if the ZLP are allowed in the FX2 firmware. I think it will work on the FX3 in the same manner.

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