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USB Superspeed Peripherals

New Contributor II

Hi All,

Please go through attached snap which is about GPIF-tool based interface definition for FPGA configuration using slave-select-parallel-map.

Now if you look at CLK to GPIO[16] that is nothing but schematic-wise it is common 100MHz clock frequency. It is derived from 100 MHz clk-oscillator and sends 100 MHz to both FPGA and FX3 chip.

Now if you look at FX3 GPIO[27] pin to FPGA CCLK pin which provides clock frequency when FX3 writes FPGA bin file into it.

My worry is that i dont know how this GPIO[27] generated 100 MHz clock frequency ? I went through GPIF design, but no-where found relationship between GPIO[16] and GPIO[27]. Then how it provides 100 MHz clock ? where it is defined or configured to do so ?

Please let me know, it'll be very helpful for me.

Thanks,

Premji

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Moderator
Moderator

Hello Premji,

GPIO 16 is used for clock pin. This can operate up to 100 MHz.

It can be clock provided to FX3 by external processor (FPGA to FX3) or FX3 providing to external processor ( FX3 to FPGA).

Rest all pins are used as Control and data pins.

You cannot use GPIO 27 as a clock, which is similar to GPIO 16.

It can only work as a control signal. The frequency of the GPIO 27 depends on state change in GPIF II SM.

There is no relation between GPIO 16 and GPIO 27 (any other GPIO).

i.e. In the attached interface (by you), the GPIO 27 output can be changed as per the states defined in GPIF II SM.

This can be defined as per the FX3 FPGA interface requirements.

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Moderator
Moderator

Hello Premji,

GPIO 16 is used for clock pin. This can operate up to 100 MHz.

It can be clock provided to FX3 by external processor (FPGA to FX3) or FX3 providing to external processor ( FX3 to FPGA).

Rest all pins are used as Control and data pins.

You cannot use GPIO 27 as a clock, which is similar to GPIO 16.

It can only work as a control signal. The frequency of the GPIO 27 depends on state change in GPIF II SM.

There is no relation between GPIO 16 and GPIO 27 (any other GPIO).

i.e. In the attached interface (by you), the GPIO 27 output can be changed as per the states defined in GPIF II SM.

This can be defined as per the FX3 FPGA interface requirements.

View solution in original post

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New Contributor II

Thanks a lot !

Definitely it gave me hint and now I can understand. However, still need to study more on this from FX3 TRM.

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