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USB Superspeed Peripherals

New Contributor

Hi 

I have a custom board with CYUSB3014-BZXC interfaced with Xilinx ultrascale  fpga for which I am facing some issue with gpif interface. I have the a working gpif inteface on a previous board in which  CYUSB3014-BZXC is interfaced with Xilinx artix fpga. In the new board with ultrascale , i am reusing the fx3 image and the fpga code ( fx3 interface part is same). However when I do a slave read with GPIF interface , I see that the FX3 is not receiving the data from the FPGA. I have probed on the data lines and pclock  signals. Clock is fine at 100MHz and data is also coming out of the FPGA. Other signals like SLCS, SLWR,SLRD,address , pktend etc are also in their expected state. I am doing a 16384 length transfer and the watermark is kept at 16380. However i note that both FlagA and FlagB are staying high throughout and not going to 0. I have a doubt that the Fx3 fifo pointer is not getting incremented or the GPIF state machine is somehow stuck. I do not have access to UART pins. They are connected to the FPGA. Any pointers as what might be happening will be really helpful.

Thanks and regards

Nithin

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Moderator
Moderator

Hello Nithin,

Please let us know the following to understand the problem better:

1. Are you using the default AN65974 firmware and state machine or have you made any changes on top of it? If you have made any changes, please let us know the changes or please share the project for us to check.

2.  Please let us know if you are trying to do a Slave FIFO Read or Slave FIFO write. This is because, from your description, you are trying to receive data from FPGA which is a Slave FIFO write operation. But you have mentioned that you are trying to do a Slave Read. Please refer to Sections 5.1,5.2 and 5.3 of the Application Note AN65974 to understand more about Slave FIFO read and Slave FIFO write. The link to the same is given below:

https://www.cypress.com/file/136056/download

3. Please probe the interface signals (address, PCLK, SLRD, SLCS, SLWR etc) and share it with us for checking at our end.

4. How are you trying to send/receive data on the host side? Is it using control center application? If yes, what happens when you try to read or write data from/to an endpoint?

Best Regards,
Jayakrishna
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Moderator
Moderator

Hello Nithin,

Thanks for sharing the project files with us for review.  As per the project, you are using P Port Socket 0 for receiving the data from FPGA. This data is read out by the host through the IN endpoint 0x81. As you are obtaining Error code 997 in control center while you try to read data from the endpoint 0x81, we can understand that the endpoint does not have any data to sent to the host. The state of flags confirm that the DMA buffer is not full. Please provide answers for my questions below for further debugging:
1. As I understand, the only difference between working and non working board is that the non working board makes use of GPIO 31 and 32 for Flag C and Flag D respectively. Please let me know what exactly are these GPIOs. Please let me know if there are any other changes between working and non working boards.

2. Please confirm that all the timings mentioned in Figure 4 of AN65974 is matching with your design. Example tAH, tAS etc.

3. I find from the ILA traces that the write signal is de-asserted before any flag activity. Please let me know how is the WR signal de-asserted? Also, please let us know the amount of data sent from FPGA to FX3 as a part of FIFO write operation.

4. Also, in the original description, you mentioned that the interface frequency is 100MHz. If this is the case, then please change the following line 

clkCfg.setSysClk400 = CyFalse; 

to

clkCfg.setSysClk400 = CyTrue;

5. Is it possible to use the default AN65974 project for testing? 

6. Can you please probe the interface signals using an external logic analyzer (not using ILA) and share the captures for us to check? 

Also, flags are used to indicate the FIFO status only. It is not used for any other purpose.

Best Regards,
Jayakrishna
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