fx3 gpif data transfer failure

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fx3_user
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Hi 

I have a custom board with CYUSB3014-BZXC interfaced with Xilinx ultrascale  fpga for which I am facing some issue with gpif interface. I have the a working gpif inteface on a previous board in which  CYUSB3014-BZXC is interfaced with Xilinx artix fpga. In the new board with ultrascale , i am reusing the fx3 image and the fpga code ( fx3 interface part is same). However when I do a slave read with GPIF interface , I see that the FX3 is not receiving the data from the FPGA. I have probed on the data lines and pclock  signals. Clock is fine at 100MHz and data is also coming out of the FPGA. Other signals like SLCS, SLWR,SLRD,address , pktend etc are also in their expected state. I am doing a 16384 length transfer and the watermark is kept at 16380. However i note that both FlagA and FlagB are staying high throughout and not going to 0. I have a doubt that the Fx3 fifo pointer is not getting incremented or the GPIF state machine is somehow stuck. I do not have access to UART pins. They are connected to the FPGA. Any pointers as what might be happening will be really helpful.

Thanks and regards

Nithin

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fx3_user
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Hi Jayakrishna,

We replaced the FX3 device in one of the boards and after that we are able to see data transfer from FPGA to PC through FX3. We will try replacing the FX3 in  other board also to check if this resolves the issue. I will update the status after some more debug.

Thanks and regards

Nithin

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JayakrishnaT_76
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Hello Nithin,

Please let us know the following to understand the problem better:

1. Are you using the default AN65974 firmware and state machine or have you made any changes on top of it? If you have made any changes, please let us know the changes or please share the project for us to check.

2.  Please let us know if you are trying to do a Slave FIFO Read or Slave FIFO write. This is because, from your description, you are trying to receive data from FPGA which is a Slave FIFO write operation. But you have mentioned that you are trying to do a Slave Read. Please refer to Sections 5.1,5.2 and 5.3 of the Application Note AN65974 to understand more about Slave FIFO read and Slave FIFO write. The link to the same is given below:

https://www.cypress.com/file/136056/download

3. Please probe the interface signals (address, PCLK, SLRD, SLCS, SLWR etc) and share it with us for checking at our end.

4. How are you trying to send/receive data on the host side? Is it using control center application? If yes, what happens when you try to read or write data from/to an endpoint?

Best Regards,
Jayakrishna
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JayakrishnaT_76
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Hello Nithin,

Thanks for sharing the project files with us for review.  As per the project, you are using P Port Socket 0 for receiving the data from FPGA. This data is read out by the host through the IN endpoint 0x81. As you are obtaining Error code 997 in control center while you try to read data from the endpoint 0x81, we can understand that the endpoint does not have any data to sent to the host. The state of flags confirm that the DMA buffer is not full. Please provide answers for my questions below for further debugging:
1. As I understand, the only difference between working and non working board is that the non working board makes use of GPIO 31 and 32 for Flag C and Flag D respectively. Please let me know what exactly are these GPIOs. Please let me know if there are any other changes between working and non working boards.

2. Please confirm that all the timings mentioned in Figure 4 of AN65974 is matching with your design. Example tAH, tAS etc.

3. I find from the ILA traces that the write signal is de-asserted before any flag activity. Please let me know how is the WR signal de-asserted? Also, please let us know the amount of data sent from FPGA to FX3 as a part of FIFO write operation.

4. Also, in the original description, you mentioned that the interface frequency is 100MHz. If this is the case, then please change the following line 

clkCfg.setSysClk400 = CyFalse; 

to

clkCfg.setSysClk400 = CyTrue;

5. Is it possible to use the default AN65974 project for testing? 

6. Can you please probe the interface signals using an external logic analyzer (not using ILA) and share the captures for us to check? 

Also, flags are used to indicate the FIFO status only. It is not used for any other purpose.

Best Regards,
Jayakrishna
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Hi Jayakrishna,

Thanks for the reply.

1. These GPIO's are not connected to anywhere else. They just go to the FPGA. The intention was to use them as FLAGC and FLAGD. However from the GPIF designer I understood that they cannot be used as FLAGC and D. Hence now these 2 GPIOs are not used inside the FPGA code.

2. The timing is met. I am actually sampling these signals with pclk in the ILA screenshot and they appear correctly. Also they are changed based on a 180 phase shifted clock. Hence I assume that we have sufficient margin.

3. In the FPGA state machine, adc_start is the signal that imitates data transfer from fpga to fx3. Attaching the statemachine .

4. ok

5. no.. fpga is controlled by i2c writes from Fx3. So i need that part of the code to instantiate transfer from fpga.

6. I have access only to data lines. other signals are routed in internal layers without vias.

Regards

Nithin

 

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JayakrishnaT_76
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Hello Nithin,

Please find my comments below:

1. From the snapshot of the state machine implemented on FPGA side, I understand that the signal adc_xfr_enable_r is responsible for initiating the Slave FIFO write. Also, flag_a_r is the ready flag corresponding to thread 0 and flag_b_r corresponds to the watermark flag corresponding to thread 0. Please correct me if my understanding is wrong.

2. At the start of transfer, only ready flag need to be used. Similarly for terminating the transfer, watermark flag only needs to be used.  So, the transition equation from stream_in_wait_flag to stream_in_write should only check if flag_a_r is high.

3. From the snapshot of the ILA traces shared before, the WR signal is made HIGH without any change in flag status. Please find this snapshot below:

JayakrishnaT_76_0-1610939263293.png

Please let us know how is the WR signal de-asserted (made HIGH) in this case. I understand from the FPGA state machine that WR will be de-asserted only when the partial flag goes LOW. This does not happen as per the ILA traces.

3. Please let us know how many bytes of data is written from FPGA to FX3. I find that the DMA buffer size allocated for the channel from P Port to U Port in the firmware is 16KB. If the FPGA is not sending enough data to FX3 (16KB), then the buffer will not be sent to the USB socket.

4. Is it possible to test the transmission of a short packet or ZLP and share the results.

Best Regards,
Jayakrishna
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fx3_user
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Hi Jayakrishna,

1. you are correct.

2. In section 11.4.2  of AN65974 , Stream IN Example [FPGA writing to Slave FIFO] , it was mentioned that FPGA will wait till flag b =1 and starts writing to the interface when flag_B = 1.

3. FPGA is sending 16kB of data from BRAM(full bRAM size). I have a counter inside the state machine to count the samples and in turn help to de assert the WR signal( missed it on the state machine). Since the value is hardcoded in FX3 as well as FPGA, we will hav e to make some changes to do that. I will try to the same.

4. Will need to see the modifications required.

In general if timing is met and the data is coming out of the FPGA, why is it not getting registered in the FX3 FIFO ? Do you suspect the  issue is at FPGA code side?

Regards

Nithin

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JayakrishnaT_76
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Hello,

Generally, we have seen issues like FX3 DMA buffers not filled with data in a slave fifo application due to the following reasons:

1. When the interface timings do not match.

2. When the interface signals are not properly provided to FX3. It is due to this reason that I asked to probe the signals externally using a logic analyzer. We have also seen cases where the signals sampled by ILA were different when compared to the signals sampled by an external oscilloscope.

Can you try sending a vendor command to FX3 the handling of which will return the current state of the GPIF state machine?  As you might be knowing, the current state of GPIF state machine can be obtained by using the API CyU3PGpifGetSMState(). More information on the same will be found in the FX3 API Guide. This will help us to understand if the state machine is stuck in a particular state or not.

Best Regards,
Jayakrishna
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Hi jayakrishna,

Can you please share the link for CYAPI guide. Is this the file you meant ?

https://www.cypress.com/file/53106/download 

Anyway I tried the CyU3PGpifGetSMState() as given below.

 case STATE_MACHINE_STATUS:
    status =CyU3PGpifGetSMState (&SMState);
    if (status == CY_U3P_SUCCESS)
    {
     CyU3PUsbSendEP0Data(1, (uint8_t *) SMState);
    }
    if (status == CY_U3P_ERROR_NOT_CONFIGURED)
    {
     CyU3PUsbSendEP0Data(1, (uint8_t *) 0x99);
    }
    isHandled = CyTrue;
   break;

with vendor req code 0xB4. However I got error code 997, while other vendor requests like VID, PID etc works fine.

Regards

Nithin

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JayakrishnaT_76
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Hello Nithin,

The FX3 API guide comes along with FX3 SDK and can be found in the following location after installation of the SDK:

C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\doc\firmware

Please let us know if the API CyU3PGpifGetSMState() and CyU3PUsbSendEP0Data() returned errors. As you do not have the possibility for debugging the firmware using UART, you can test by making use of the API CyU3PDeviceReset(CyFalse);. If this line of code is executed anytime, the device will enumerate again as Fx3 Bootloader device in the control center.

Also, can you please share the modified firmware having he implementation of vendor command for us to check at our end?

Best Regards,
Jayakrishna
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fx3_user
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Hi Jayakrishna,

CyU3PUsbSendEP0Data()returns 0 before and after initating the data transfer from fpga to fx3. CyU3PGpifGetSMState() returns CY_U3P_SUCCESS ( verified by returing different values for success and fails).

Thanks and regards

Nithin

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JayakrishnaT_76
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Hello,

As per my understanding, after the modification of following line of code:

CyU3PUsbSendEP0Data(1, (uint8_t *) SMState);

to 

CyU3PUsbSendEP0Data(1, &SMState);

you are able to get the current state of the state machine in response to the vendor command. Please correct me if my understanding is not correct. Please let me know the state number so that we can understand the issue better. Please share the snapshot of the control center application having the response of the vendor command sent to the device for obtaining the current state.

Best Regards,
Jayakrishna
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fx3_user
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Hi Jayakrishna,

Your understanding is correct. I am getting the state number as 0 - reset state. Attaching the control center image having the vendor command response.

Regards

Nithin

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JayakrishnaT_76
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Hello Nithin,

Please let us know the following information:

1. When was the vendor commands sent to return the state of the state machine?

2. Did you test the same with multiple boards? Did you see the same results on all the boards?

3. What are the differences between working and failing boards. Please let us know all the differences.

Also, it seems that the GPIF state machine is not started as CyU3PGpifGetSMState() returns 0. To confirm if this is correct, can you please try toggling a GPIO in the state IDLE using GPIF II designer. Then probe that GPIO and check if it is toggling or not?

Best Regards,
Jayakrishna
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fx3_user
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Hi Jayakrishna ,

1. In the previous attachment the last 2 transfers shown were for this particular vendor request.

2. Yes. I have tried with2 boards. both return the same state of 0. 

3.  The working and failing boards are 2 completely different set of boards in which the usb interface is same - 

differences between the 2 relative to fx3.

in the failing board - FLAgC and  D are left unconnected.

In the failing board FX3 VDD is at 1.2v where as in the working board FX3 VDD is at 1.8V ( which should be wrong according to the datasheet)

no other differences in the fx3 connections.

In the GPIF designer 2.0 I don't see drive gpio as a state like described in the user guide. Attaching the screenshot of the GPIF designer tool for reference.

thanks and regards

Nithin

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Hello,

Please let us know when the vendor commands were sent to the device for retrieving the state of the state machine? Was it when the FPGA was transferring data to the device? Or was it before the start of transmission of data from the FPGA? 

Also, for driving a GPIO from GPIF II designer, the following needs to be done:

1. In the interface definitions tab,  under interface settings, change the no of output signals from 0 to 1 as shown below:

JayakrishnaT_76_0-1611052899032.png

2. Now, click on the drop down and select the required GPIO as shown below:

JayakrishnaT_76_1-1611052944082.png

Double click on OUTPUT0 to change the name of the signal and other signal settings (assert/toggle, polarity etc).

3. After this, switch to the state machine tab. You will find DR_GPIO action in the Actions List as shown below:

JayakrishnaT_76_2-1611052991703.png

4. Drag and drop this action to the idle state.

Please let me know if you have any queries on this.

Best Regards,
Jayakrishna
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fx3_user
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Hi Jayakrishna,

We replaced the FX3 device in one of the boards and after that we are able to see data transfer from FPGA to PC through FX3. We will try replacing the FX3 in  other board also to check if this resolves the issue. I will update the status after some more debug.

Thanks and regards

Nithin

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