We are using the FX3 device to transfer data between FPGA and a PC. The system use the synchronous Slave FIFO interface at 100MHz with 3 endpoints.
(Auto mode DMA: CY_U3P_DMA_TYPE_AUTO)
We have noticed that if changing the size of the DMA buffer from 1024 to 32768 the last two words (8 bytes) are always corrupted!
Could you please check it?
Can you probe the last 8 bytes and compare with the data received in the DMA buffer? You can see that by getting the handle of the buffer in the DMA callback and print them using debug messages.
Have you checked this using AN65974 example firmware. Here we have only 2 endpoints, but once you test it, you can add another endpoint and the required functionality.
I understand that you are familiar with AN65974 firmware. Do you see the issue with the same AN65974 setup & firmware as well?
As you have pointed out that the data in the DMA buffer itself is wrong. Can you probe the data lines on the GPIF interface and record for the last two bytes? We need to see the setup/hold requirements at the interface and whether the FPGA is providing the correct signal and data.
We are using our own hardware, but with your auto mode DMA (CY_U3P_DMA_TYPE_AUTO).
During investigating the issue we have found that it looks like some of the bits between the two last bytes are swapped within the FX3!
For debugging this issue, I request you to use a manual channel so that you can print the see the content of the DMA buffer. Were you able to probe the last 2 bytes? and compare it with the DMA data?