USB Superspeed Peripherals

Hi,

I am facing an issue with SDK 1.3.4 while using multi thread. I have ported a project source to SDK 1.3.4 that I already used in SDK 1.3.1. I have not changed anything in my source code, I just build the source with 1.3.4. 

In firmware we are just getting commands from HID call back, once I received command in HID call back I will set a event and in another thread I will wait for that event once I received the event I will perform my things. This simple concept is not working if I build my project in SDK 1.3.3 or SDK 1.3.4. Please help us to solve this issue at earliest.

Thanks and Regards,

Vignesh Kumar R.

Hello,

I can't speak English well.

In the FX3 SlaveFIFOSync 5Bit example, we want to use 6 ENDPOINTs.

endpoints 0x1, 0x2, 0x3 works well.

But endpoints 0x81, 0x82, 0x83
BULK IN transfer
BULK IN transfer failed with Error Code:997 occurs.

I checked the 5bit FIFO ADDR
From 0 to 31, the flag of the INPUT endpoint did not occur.

Only output endpoint 0x1~0x3 operates.

If you change the positions of CY_U3P_PIB_SOCKET_0 and CY_U3P_PIB_SOCKET_4, this time they all change to INPUT and OUTPUT does not work.

Can you explain what the problem is?

I want to use all 6 ENDPOINTs

Thank you.

Hi,

according to this thread https://community.cypress.com/t5/USB-Superspeed-Peripherals/FX3-change-packet-size-in-ISOC-module-USBIsocSourceSink/m-p/206286#235342

i was able to change the CY_FX_ISO_MAXPKT parameter.

when Running OUT Traffic (from the EP_OUT) from the streamer GUI, i was able to see in USB3 Trace that the Data len that my host is sending is actually the one that i defined in CY_FX_ISO_MAXPKT parameter.

my problem here is when i want to test the other way, IN_EP from the streamer GUI.

when choosing the IN_EP from the Streamer GUI and press on start, im able to see that there is traffic but in the USB3 Trace i see that the Data Len that the FX3 sending is always 0 no matter what CY_FX_ISO_MAXPKT is configured.

only when CY_FX_ISO_MAXPKT = 1024 i able to see that the FX3 is success to send ISOC Data Packet with Len = 1024 (verified it in the USB3 Trace).

is there something else that i need to configure? or maybe i miss something here? 

more details (from the USBIsocSourceSink module) :

/* ISO Mult settings for SS and HS operation. */
#define CY_FX_ISO_PKTS (1)

/* Burst length in packets supported by the ISO endpoints, when operating in USB 3.0 mode. */
#define CY_FX_ISO_BURST (1)

/* Dma buffer size multiplier. As ISO endpoints will only transfer ISO_PKTS * ISO_BURST packets of data in*/
/* each interval, this can be set to 1 without any performance limitation. */
#define CY_FX_DMA_MULTIPLIER (1)

Hi,
I used cyfxuartlpdmamode example and modified the channel to UART-> CPU ( MANUAL IN) and another channel CPU ->UART (MANUAL OUT). I attached my new firmware.  I used the UART event(UartIsr). I send data from Teraterm, I got ISR after sending 16-bytes(DMA size). I put a fixed buffer, when I got the ISR, I send that data to Teraterm. Up to here, everything is ok. But I have 2 problems:
1- I don't get another ISR. I mean I sent 16 bytes first time, I got letters A to Q (fixed buffer) in Teraterm, but again I entered another 16 bytes and I expected to get another ISR, but I don't get. I think the previous event hasn't had clear, and I don't know how I should do that.(SendDebugMessage(buf, len))

2- When I try to replace the fixed buffer with the input buffer, I got nothing. (SendDebugMessage(buf_p.buffer, len))

Could you please help me on this matter?

Thanks

Hi all,

I am very new to the FX3 and I am trying to stream data from a 32 bit bus sampled at 10MHz to the computer. Data is sampled on the GPIF using two alternating threads. A program written on linux using libusb and cython simply reads 2MB of data (for now) and dumps it to the disk. 

Currently, I have a testbench set up to generate a 16-bit binary counter to be sampled. However, looking at the dumped data returned, there are (seemingly random) gaps in the data where the counter will jump values. I cant seem to find any consistency as to where the data drops and how much will be lost. 

Is there any way to figure out how to avoid packet loss?

Thanks!

Hi, I'am new to the CX3 environment and started to build a application for converting 1928*1088 @ 60FPS  RAW10 MIPI to USB 3.0 UVC , we are using the CX3-RDK board from E-CON systems and we are designing our own daughter board. When using the configuration tool iam getting certain errors so need a bit of clarification on it. (Attached screenshots for your reference). In Image sensor configuration the CSI Clock is it referring the MIPI PIXEL Clock coming from the sensor? in that case our sensor gives 90Mhz but providing that value the tool is expecting a minimum value around 316Mhz. Our sensor has speed of 720Mbps per lane and we are using 2 lanes so i guess the output video format can be 16bit output

After giving these settings in image sensor configuration going on to CX3 receiver configuration following errors were occurred

Also tried to change the CSI Clock to the minimum expected value and changed output configuration to 24bit which eliminated the Parallel output error (Explanation on this problem would be great), but still cant achieve output pixel clock properly. 

Is my configuration is proper? if not what iam missing?

I'm feeling a little out of my depth here as I'm a System Administrator rather than a seasoned Electronics Engineer, I hope this question makes sense...

I am trying to upgrade two machines, that each have several Cypress Westbrige devices attached to them, from Ubuntu 16.04 to Ubuntu 20.04. With Ubuntu 16.04, all devices enumerate correctly first as 04b4:00f3 and then go on to download their custom firmware, detach and reattach. However, with 20.04 I get the following errors:

Feb 23 12:05:47 master kernel: usb 1-6-port1: status 0101, change 0000, 12 Mb/s
Feb 23 12:05:47 master kernel: usb 1-6-port1: indicator auto status 0
Feb 23 12:05:47 master kernel: usb 1-6.1: new full-speed USB device number 3 using xhci_hcd
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:47 master kernel: usb 1-6.1: new full-speed USB device number 4 using xhci_hcd
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:48 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:48 master kernel: usb 1-6-port1: attempt power cycle
Feb 23 12:05:48 master kernel: usb 1-6-port1: not enabled, trying reset again...
Feb 23 12:05:48 master kernel: usb 1-6.1: new full-speed USB device number 5 using xhci_hcd
Feb 23 12:05:48 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:48 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: device not accepting address 5, error -71
Feb 23 12:05:49 master kernel: usb 1-6.1: new full-speed USB device number 6 using xhci_hcd
Feb 23 12:05:49 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: device not accepting address 6, error -71
Feb 23 12:05:49 master kernel: usb 1-6-port1: unable to enumerate USB device

Two other similar devices connected to this machine at 1-6.3 and 1-6.4 show identical errors.

I have tried:

• using 'uhubctl' to power cycle the ports of the 1-6 hub
• using 'uhubctl' to reset each of the ports on the hub
• adding the 'usbcore.autosuspend=-1' kernel parameter (after reading your KBA222372 - Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration)
• adding extra time for the device descriptor read with kernel parameter 'usbcore.initial_descriptor_timeout=10000' (10s rather than the default 5s)
• setting various combinations of 'usbcore.use_both_schemes' and 'usbcore.old_scheme_first' to change method the kernel uses to initialise USB device

Have any other users experienced similar problems Cypress FX3 based devices when running Ubuntu 20.04?

Thx

I am currently using a USB2 High-Speed FTDI chip for USB-to-SPI conversion. 

I am trying to get the lowest possible time to send multiple, small datagrams over SPI.  I am not too concerned about the time to actually send the bits (so far at least, maybe withFX3 that's a new constraint!) which is only a handful of microseconds.

To test the speeds, I perform a loop to send 6 bytes back-to-back (Windows 10, 6-core Xeon, C#) 100 times then calculate the average time with the following psuedocode:

1. Start stopwatch

2. Chip select assertion

3. Read+Write 6 bytes over SPI bus at 10 MHz clock

4. Chip select de-assertion 

5. Repeat #2 through #4 until 100 cycles are reached 

6. Stop Stopwatch

7. Calculate average total time per SPI transaction (= Elapsed time of stopwatch divided by 100)

This yields about 700 microseconds per SPI transaction (on average) when the computer is doing nothing but running this loop, so it's probably a best-case situation.

Here's my questions: 

1. If I use GPIO-controlled slave-selects with FX3, what is an estimate of the total cycle time I would see per SPI transaction (assume 6 bytes transfer, 10MHz clock)...can that 700 microseconds number drop substantially?

2. Would this be done with DMA mode or register mode?  If the number could be dropped low enough I could test with some dummy writes and an oscilloscope with an FX3 eval to ballpark it.

This isn't a legally-binding number :).

I'm just trying to estimate if it would be worth testing something with an FX3 eval board for example.  If that 700 microseconds could come down to below something like 150 microseconds I would consider spending time on it, but if you think it's not going to get that low I would pass and live with what I have.

Thanks.