USB superspeed peripherals Forum Discussions
Hello
Is there a way to detect rising edge of FV instead of detect it on high state?
I have a application where we could not relies on the FV high, but it need to relies on FV rising edge. Any possible way to detect this?
Thanks
Hello, I have created a Interface between Xilinx FPGA and CYUSB3014 FX3 controller. We are running in slave FIFO 32 bit data mode. We are transmitting a packet size of 32KB as of now from the FPGA. We want to now increase the payload to 64KB. What configurations in the source code needs to be changed on the controller side?
Show LessHello!
I am interfacing the IIS2DH sensor, and I can configure its registers and can read most of them. I have a pair of registers where I should read 2 registers one after another. For that I have to alter the lower register's address to put the IC into the auto address incrementing mode. I configured the IC and the registers based on the datasheet based on the conversation with the manufacturer I did it in a proper way. The IC's datasheet mention the proper I2C communication for the case of multiple byte read (attached that part):
I am using the FX3 based I2C communication functions:
CyU3PReturnStatus_t acc_i2c_readInc(uint8_t slave_addr, uint8_t reg_addr, uint8_t *buff)
{
CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;
CyU3PI2cPreamble_t preamble;
if ((slave_addr != ACCEL_ADDR_RD) && (slave_addr != I2C_MEMORY_ADDR_RD))
{
CyU3PDebugPrint (4, "I2C Slave address is not valid!\n");
return 1;
}
preamble.length = 3;
preamble.buffer[0] = slave_addr & I2C_SLAVEADDR_MASK; /* Mask out the transfer type bit. */
preamble.buffer[1] = reg_addr;
preamble.buffer[2] = slave_addr ;
preamble.ctrlMask = 1<<1; /* Send start bit after second byte of preamble. */
CyU3PDebugPrint (4, "Reg address%d\n",reg_addr);
apiRetStatus = CyU3PI2cReceiveBytes (&preamble, buff, 2, 0);
SensorI2CAccessDelay (apiRetStatus);
return apiRetStatus;
}
I modified the CyU3PI2cReceiveBytes function byteCount variable 1 to 2. Is this implementation is capable to read 2 bytes in an address auto incrementing situation? The buff pointer points to an array, so if I receive 2 bytes I can store it.
Best regards,
Bence
Show LessWhen I try to use the "sync slave fifo" interface of cyusb3014 to continuously and instantaneously transmit the sampled data generated by the ADC to the PC, I'm stuck with the following problems:
1. The data I receive after reaching MaxPktSize will be lost for a period of time (about 42 cycles data loss), the following is my test using a counter as data:
It can be seen that the data is missing after 0x3917B759:
2. When I read the data, there are always expired data being read to the PC instead of real-time data. These data have expired for the ADC. As shown in the above picture, triggered data can be read only when I need to click the "Transfer Data-IN" multiple times after triggering the waveform .
I hope to get the current data of the ADC when I press "Transfer Data-IN".
Hello,
I have custom PCB board which contains a FX3 mcu. I already have a working UVC firmware(the UVC part of the firmware is based on the AN75779 and uvc example project. ) where the debug module used for debug informations. The device is configured as a composite device (UVC and CDC). Now I want to send custom commands via the COM port. I modified the firmware based on the "John Hyde Design by example" book and example code (CDC_BulkLoop). But my problem is that I am not able to send commands via the COM port. For the serial communication I am using realTerm and TeraTerm. When I implemented the function which I learnt from the "CDC_BulkLoop" example, but when I try to send commands the board not responding. Now I am a bit confused how to use the CDC device. I also checked the "cyfxusbuart" example, but it did not help understand the mechanics. I attached the source files that I modified in the UVC example project, and image which shows the CDC descriptors of the device.
Best Regards,
Bence
Show LessAre there any examples of interfacing FX3 to two different video streams, each with their own clocking?
Specifically, are there any examples, references or application notes that might present creative solutions or identify potential issues when attempting to interface, buffer or adjust to I/Os with different clock domains using the FX3?
Greg
Show LessI'm sending a test pattern (ramp) from an FPGA using the GPIF data bus to the FX3.
The data arrives fine, but when I read the data from my Windows application there are big blocks of zeros in the data, as seen in the picture below.
What could be causing this?
I can't see any zeros added on the FPGA side.
I expect that the read length returned from FinishDataXfer should make sure that that part of the buffer should contain valid data.
Show LessHi! On my board I have a 32-bit parallel FPGA configuration interface connected to the FX3 chip. In order to use it I need to implement a synchronous master FIFO interface, I guess. The problem is that I can't make a GPIF configuration using GPIF Designer (ver 1.0) I downloaded recently. The GUI simply doesn't provide necessary options and it's different from what is presented in AN87216 (Designing a GPIF™ II Master Interface).
For example, here is the screenshot from the AN:
And here is what I have:
There are a lot less options to select and, in particular ,there is even no 'master' option I need.
Yes, It's possible to create .h file manually, but maybe there is a possibility to get that version of the GPIF Designer from the AN?
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FAQ stated that a) the space between the “P” and “N” signal tracks should be twice the width of the tracks, b) MIPI lane should have 100 ohm impedance. Is it mandatory to follow both rules or can only maintain impedance and discard the twice spacing requirement?
Show LessWe want to use FX3 as USB2 bridge for UART, I2C and SPI only.
In that case we need to turn off FX3 VIO1, VIO2, U3RXVDDQ and U3TXVDDQ according to datasheet and AN70707.
What is turn off power supplies mean?
Can we leave these power lines floating? Or should we connect them directly to VSS or via capacitor to VSS?
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