USB superspeed peripherals Forum Discussions

Hello,

    I downloaded fx3 dvk board schematics from cypress website, and I have some question about it after some days.

    On J48(usb micro B connector) in page 9, the connector and the net label on it is as follows:

    connector       net_label

-----------------------------------------

    6 (SSTX-)        SS_TX_M

    7 (SSTX+)       SS_TX_P

    9 (SSRX-)       SS_RX_P

    10(SSRX+)     SS_RX_M

------------------------------------------

From Pin 6 & 7, Tx- is labeled as TX_M, and TX+ is labeled as TX_P.

So, I suggest 'M' means 'Negative' and 'P' means 'Positive'.

But From Pin 9 & 10, RX- is labeled as 'RX_P' and RX+ is labeled as 'RX_M'.

Can someone tell me WHY? Is this correct?

(My English is so poor, sorry!)

Best, Regards.

Hallo,

      I am using the cypress usb3014 chip for my development. The usb3.0 controler of my PC is  ASMedia USB 3.0 controler,.When i am trying to connect the cypress usb3014 chip with my computer, the driver cann't work.In this case, could Cypress Development board-DVK connect with ASMedia USB 3.0 controler?

Hi,

We are designing FPGA to write data to FX3 Synchronous Slave FIFO. Our FPGA use thread 0 (A0,A1 = 00) and monitor FLAGB pin for FIFO full status. For firmware we use SlaveFifoSync example provided in SDK.

In application note AN65974[Designing with the EZ-USB FX3 Slave FIFO Interface], it mention that there are two-cycle latency incurred in current thread flag.

So we try to configure the FLAGB as dedicated thread flag for thread 0. What we modified is to change

{CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5)      , 0x00000018}, // FLAGB as the  current thread  flag

as

{CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5)      , 0x00000010}, // FLAGB as the  dedicated thread 0 flag

However, the two cycle latency are still exist after we apply this patch...

Is there any solution available to configure full flag without the latency?

Regards,

Elvis

Hallo,

I download my image file into the RAM of the FX3 with the CyControl. After that, the device dont boot, perhaps because the firmware is incorrectly. If I reset the the device, the FX3 also didtnt boot as cypress device. So that it does again, I need a reboot of the PC.

What is the problem?

My system is Win7 64 with the latest renesas driver.

Marco

Can anybody send the User Guide and Windows Driver of BENICIA DVK BOARD VER1 to rj_tang@163.com ? Thank you very much!

We have a synchronous slave fifo set up and running at 40 MHz, with the active thread selected by the A0 and A1 pins.

It seems that when starting the state machine in the RESET state, writes will always go to thread 0, even if the address pins say, for example, thread 2.  Once pktend asserts for the first time, though, the write will start going to the correct thread as specified by the pins.

We have found that by starting the state machine in IDLE, however, the first write goes to the correct thread as it should.

What is different about the RESET state such that it does not work properly, while IDLE does?

 Hi,

I am a c++ developer who has interfaced with an FTDI FT245RL.  This part allowed me to send "USB bulk" data to it that would appear out the other end to an FPGA.  Our board's FT245RL part has been replaced with a Cypress cy7c68013.

The Cypress part scares me and seems much more complicated than the FTDI... but it is so popular that this must not be true.  Can someone point me to a site/book/document that will get me up to speed?  The ideal place will answer these kinds of questions:

- FTDI part comes with a document for the digital designer (FPGA guy) that includes a pin layout explaining the data bus, the control lines, and a timing diagram.  Where can I find this information for the cy7c68013?

- Why do people seem to call the cy7c68013 by the name "fx2"?

- I use libusb's "bulk rate" messages to send/receive data to/from the FTDI.  How do I do this with the cy7c68013?

- Why does the cy7c68013 seem to require "firmware"?

- How do I (the c++ developer) get the "firmware" to the cy7c68013?

- Where do I find "firmware"?

- Is there "firmware" out there that will make my cy7c68013 behave like an FT245RL?  (Byte-at-a-time bulk rate FIFO)

I don't expect these questions to be answered by anyone here, but I would like to be shown a resource that will enlighten me.

Thank you for your help,

Chris

Hi, we designed and assembled two prototyping board mounting a ES of the EZ-FX3. The board plugs directly into a Xilinx virtex6 development board trough an FMC connector.

The “thing” is now working well end delivers 220 MB/s using the modified BulkSource reference firmware posted by aasi on this forum.

On our original board design we simple connected the 32 kHz Watchdog Timer Clock Input to ground as one would do if there is no interest  on using the watchdog functionality (also considering that in the datasheet the 32 kHz clock is referred as optional). Using this approach unfortunately the USB bus do not works. The CPU boots correctly and tries to load the firmware from the I2C (if configured so) but the load from USB simply doesn’t work since the USB interface doesn’t work.

Well, we mounted a second prototyping board but this was affected from the same problem. In the end, in order to make our system as much similar as the Cypress development board we connected the Watchdog Timer Clock input to a 32KHz clock source … and  … miracle … The USB 3 interface works perfectly, with the above mentioned performances.

My question: why is there no mention about this important detail in the FX3 datasheet ? Do we missed something ? Did somebody ever tried to use an USB 3.0 FX3 without the 32 KHz clock ?

Joel

Hello

I am using the 16 Bit slave fifo interface and set the fifo full flag of the writing tread fixed to flag B. The DMA channel is set to auto between slave fifo and usb interface, using 2048 byte buffer size with 8 packets.

I am using the BulkLoop C++ application example to send and receive data. To the slave fifo interface an FPGA is attached, that loops the data back.

Now it happens sometimes that the FX3 reports fifo full on the writing thread (flag B stays low forever), and as a result, the FPGA stops writing data to the slave fifo. If I reset the FX3 it works again flawless, but after a few seconds gets stuck once more with the same behavior. Has anybody encountered similar issues? Thx.

Silvio