USB superspeed peripherals Forum Discussions

Hi,

the release notes for SDK 1.2 state on p. 6 that there's a way now to reset the FX3 to the boot firmware image without the necessity to disconnect it.

Can you please detail how this is going to be done? Is there a particular USB vendor command to realize this functionality?

Thanks,

Markus

For more information on the FX3 + Altera Cyclone 4 Development platform, please visit http://www.cypress.com/?rID=64819.

Thanks,

Anup

Hello,

tCFLG is increasing if I decrease PCLK frequency. Is this true?

If yes what is the maximum value of tCFLG at 100 MHz?

Regards,

I am trying to use the DMA suspend/resume API  to work around the FX3 silicon bug that causes incorrect PIDs to go out on ZLPs for high-bandwidth isochronous endpoints (http://www.cypress.com/?app=forum&id=167&rID=62980). This is for UVC, so the DMA channel is configured as TYPE_MANUAL.

In my DMA callback, at a point where I know there are no packets pending for USB transmission (i.e. the video stream has temporarily "bottomed out" and there is a risk of ZLPs being sent), I call

   CyU3PDmaChannelSetSuspend( CY_U3P_DMA_SCK_SUSP_NONE, CY_U3P_DMA_SCK_SUSP_CUR_BUF)

Based on the API documentation I expect to receive a DMA callback of type CY_U3P_DMA_CB_CONS_SUSP, but one never comes.

Is it not possible to suspend a MANUAL socket that is active but effectively idle? Does the HW require a DMA buffer to be committed before it will honor the suspend request? The documentation is fuzzy on this point, and I don't see any examples relating to DMA suspend/resume.

I would like to use a 32 bit wide synchronous slave FIFO interface with my FX3 circuit. This reserves a large number of pins.

Before the slave FIFO interface is put into operation, I would like to borrow two or three of these pins (marked GPIO) in order to have enough pins to configure my FPGA. Can I temporarily configure these pins as Simple IO, on the fly even after the GPIO-2 configuration data has been loaded? Or does the GPIO-2 configuration data override?

The FX3 JTAG port has internal pullups of 50k on all connections except TCK which has a 10k pulldown, according to the data sheet.

The FX3 devkit PCB has 10K pullup resistors on all these pins. Is the conflict on TCK intended? And if I want to use the same JTAG debug cable on my own board as on the devkit, is this arrangement what is required?

Hey anyone,

I'm just not finding that the PC application sources supplied for the FX3 development kit are cutting it as a starting point for a Windows application. The C++ projects require MFC libraries and my compiler does not support it. The C# apps are, well C#... Does anyone have a nice old C/C++ application with source that shows the basics of what needs to be done to setup and transfer data to/from superspeed endpoints? Nothing fancy is needed, I just want to verify exactly what is being sent back and forth. I know from my logic analyzer in my FPGA that it isn't always what the Cypress supplied applications are telling me. I can write C code to get the functionality that I want.

Hi. Can anyone import the development board schematic and pcb in altium designer and then post the Altium Designer files? It's a quick job, if you have both (altium designer and Alegro installed).

Thanks René

Hi everyone