I have a software (c++) using the v126.96.36.199 version of the CyUSB3 driver (.sys). This software is statically linked with the CyAPI.lib delivered with this driver.
Now, I want to use the latest CyUSB3 driver (v188.8.131.52) with the same software. Do I need necessary to link the software with the CyAPI.lib delivered with this latest driver or I can keep my software as well (<=> no change has been done to the CyAPI.lib) ? In fact, I don't want to generate a new version of my software if not needed.
I am sending/receiving data to/from UART to bulk end points. Every thing works well when I use control center.
But when I use the same setup with cyusb_linux instead of CC, I can only send data. When I hit the receive button, I got error -7 in cyusb_bulk_transfer (on_pb6_rcv_clicked). and it shows "Bytes read from device = 0". Could you please give me some clue to find the problem.
I am trying to modify the cyUSB3,ini file inrder to use our own VID & PID values,
I followed the steps in "Cypress CyUsb3.sys Programmer's Reference" section "Modifying CyUSB3.INI"
but the device is not recognized and I get the following message
"the hash value for the file dose not exist in the specified catalog file. The file is probably damaged or has been tampered without permission"
How could I overcome this problem?
During write transfer (Fx3 to PC), despite having full buffer (indicated by asserted DMA READY flag). After partial flag is asserted i keep writing 3 more data words, watermark value is 3 and I have 16-bit data bus. I used following formula from AN65974 app note: watermark x (32/bus width) –3.
In attachment I send firmware with GPIF project.
I found in CyUsb3.pdf the instructions to configure the inf file, although I don't have much experience with inf files in general. I've added my devices VIDs and PIDs, and they enumerate properly, so that's a good start.
I'm currently trying to get the script feature to download the firmware into the FX3 when it attaches. I have it in a state where it creates the registry entry that points to the script location, and I've made sure that folder exists (and it is a subdirectory of System32). If I copy the script manually, it runs and downloads the firmware when the FX3 connects, so that's excellent. The trouble is that it doesn't copy the script into that location when I install the driver.
Is it supposed to copy the script, or am I supposed to do it myself? If so, what have I missed?
While I'm on the topic, is there any way to make the INF file create the folder if it doesn't already exist, or am I on my own for that? It seemed from other answers I saw that it might not be possible to create the folder from the INF file.
I'll attach the files so you can see what I've done so far.
Last time i issue a problem is :
but it closed, so i create a new question for continue debug.
Since i set:
FX3_UVC_ISO_PAYLOAD_SIZE = ((FX3_EP_ISO_VIDEO_SS_BURST + 1) * (FX3_EP_ISO_VIDEO_SS_MULT + 1) * 1024) = (0x07+1)(0x01+1)*1024=16k
0x01, /* Servicing interval for data transfers */
It means cypress will report max palyload size is 16k, bandwidth is 16kB/125us *8= 1Gbps. and i capture usb package:
It is correct. Could i reduce the bandwith further?
How i reduce the wBytesPerInterval and open camera successfully?
We have been using CYUSB3014-BZXI and EZ-USB FX3 SDK 1.0 version.
The problem is it takes long time (about 250msec) in function CyU3PUartTransmitBytes.
We send 7Bytes, it takes more than 250msec. I think the time is derived from the wait time in CyU3PUartTransmitBytes before actually sending UART.
How to improve the UART transfer speed?
Thanks for your quick response in advance.
SX3 software is currently supported by EZ-USB SX3 Configuration Utility. Do you plan to release an FX3 like Software Development Kit for SX3?
As I understand the SX3 preliminary datasheet, the SX3 could solve a limitation of the FX3, where SPI interface is available with 32-bit GPIFII interface. However, I may be wrong and SPI interface is only available for firmware boot and FPGA init, like in FX3.
For example: in a high bandwidth streaming application with JESD204 ADCs or DACs over the 32-bit GPIF interface of an FX3, the FX3 is left with UART and I2C interface to control the JESD204 devices, which typically have an SPI control interface. Even if you bridge UART or I2C into SPI interface, you loose bandwidth and increase latency. You do not want to use GPIFII for data streaming and control, because that adds potential risk of loosing JESD204 data.
I thought the SX3 was a perfect candidate to solve that problem, but I fear it is intended to be a simple subset of the FX3.
If SX3 can not support SPI and 32-bit GPIFII interface at the same time, I hope you consider these type of applications with FX3G2 and FX3G2D.Show Less
When I use GPIF-II sync slave fifo interface with 2-bit address mode, I can successfully set watermark values for the four threads / P-port sockets. Just like the following:
CyU3PGpifSocketConfigure (0, CY_FX_PRODUCER_1_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (1, CY_FX_PRODUCER_2_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (2, CY_FX_PRODUCER_3_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (3, CY_FX_CONSUMER_1_PPORT_SOCKET, 5, CyFalse, 1);
And now, I switch to 5-bit address mode for more transfer endpoints. And I want to set watermark values for each P-port sockets. Here are fourteen P-ports. However the following code is not availbale.
CyU3PGpifSocketConfigure (0, CY_FX_PRODUCER_1_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (1, CY_FX_PRODUCER_2_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (2, CY_FX_PRODUCER_3_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (3, CY_FX_CONSUMER_1_PPORT_SOCKET, 5, CyFalse, 1); CyU3PGpifSocketConfigure (0, CY_FX_CONSUMER_2_PPORT_SOCKET, 5, CyFalse, 1); CyU3PGpifSocketConfigure (1, CY_FX_CONSUMER_3_PPORT_SOCKET, 5, CyFalse, 1); CyU3PGpifSocketConfigure (2, CY_FX_PRODUCER_4_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (3, CY_FX_PRODUCER_5_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (0, CY_FX_PRODUCER_6_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (1, CY_FX_PRODUCER_7_PPORT_SOCKET, 6, CyFalse, 1); CyU3PGpifSocketConfigure (2, CY_FX_CONSUMER_4_PPORT_SOCKET, 5, CyFalse, 1); CyU3PGpifSocketConfigure (3, CY_FX_CONSUMER_5_PPORT_SOCKET, 5, CyFalse, 1); CyU3PGpifSocketConfigure (0, CY_FX_CONSUMER_6_PPORT_SOCKET, 5, CyFalse, 1); CyU3PGpifSocketConfigure (1, CY_FX_CONSUMER_7_PPORT_SOCKET, 5, CyFalse, 1);
Then no data can be transfered through any P-ports.
So, I wonder what's the correct way to assign watermark values for P-ports - under 5-bit address mode.
Hi, I'm making code to test i2c write operation.
FX3 is sending out data to external FPGA through i2c and if FPGA receive data, turn on the led connecting FPGA.
But when I check the i2c signal on the signal analyzer program,
the i2c scl clock is stopped after sending the device address.
The device address of FPGA is 0x70.
And this is my i2c write code.
If you know what's the problem, please let me know.