USB superspeed peripherals Forum Discussions

I am using the GPIF empty flag fixed to thread 0 to notify a FPGA when to start a data transfer to the FX3. The FPGA uses the address bus to dictate which thread the data should go to and it is also fixed to thread 0. The FPGA waits for the empty thread to assert before sending any data and I can see that the flag does assert however the flag doesnt unassert when expected. Instead, the flag stays low even after data should be written to the FIFO. I am not sure why the flag is staying asserted. Reading the documentation it doesnt say any firmware setup is required and the GPIF configuration is as follows: Thread_0_DMA_Ready flag, Initial Value High, Active Low Polarity. I have included an ILA photo of what I see during an attempted streaming. Note that no data is ever received by the USB host and the firmware doesnt recognize any production callbacks either. We have gotten data transferring between the FPGA and FX3 before and have done nothing to interfere with that.

我使用FPGA产生行信号同步和场信号同步信号，使用的GFIF时钟为90MHZ，32bit。当DMA缓冲区大小设置为16kB、个数为4时，最大只能到达1920*1080*30fps；当DMA缓冲区大小设置为48kB、个数为2时，最大只能到1920*1080*60fps。以上是我的测试结果，我想知道如何设置DMA缓冲区大小(CY_FX_UVC_STREAM_BUF_SIZE)、个数(CY_FX_UVC_STREAM_BUF_COUNT)以及传输端点的突发长度大小(CY_FX_EP_BULK_VIDEO的endPointConfig.burstLen)，才能达到1920*1080,80fps的速率，理论上90MHZ可以达到90MHZ*32bit/8/1024/1024=343MB>1920*1080*2*80/1024/1024=316MB。

另外，对于AN75779中的UVC固件是不是不支持GPIF为100MHZ，我使用1920*1080*30fps测试时，GPIF设置为100MHZ，调整好行信号同步和场信号同步信号的消隐时间，但是串口显示的部分DMA缓冲区数据（dmaBuffer.count）不是固定的，这是不正常的，我想知道为什么？

Dear Friend：

I am using cyusb3014 to implement UVC camera, my image data sent to the host, I found that sometimes the image will flicker, the frame rate is not stable; I use variables in the DMA interrupt to track data and print through the serial port, I found that sometimes a frame of the packet is incomplete, will lose 2 buffer of data, I add IO control in the DMA interrupt, I detect the DMA interrupt by measuring IO changes

My DMA interrupt program is shown below：

void CyFxUvcApplnDmaCallback ( CyU3PDmaMultiChannel *chHandle, CyU3PDmaCbType_t type, CyU3PDmaCBInput_t *input)
{
CyU3PDmaBuffer_t dmaBuffer;
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
static uint16_t FullBuffer1 = 0;
uint32_t InterData = 0;

InterData = CyU3PVicDisableAllInterrupts();

if (type == CY_U3P_DMA_CB_PROD_EVENT)
{
CyU3PGpioSetValue(FX3_CTL50_OUT, 1);

status = CyU3PDmaMultiChannelGetBuffer (chHandle, &dmaBuffer, CYU3P_NO_WAIT);
while (status == CY_U3P_SUCCESS)
{
/* Add Headers*/
if (dmaBuffer.count == (MaxData - 16))
{
#if DataTracking
FullBuffer1++;
#endif
/* A full buffer indicates there is more data to go in this video frame. */
/* Copy header to buffer */
CyFxUVCAddHeader (dmaBuffer.buffer - CY_FX_UVC_MAX_HEADER, CY_FX_UVC_HEADER_FRAME);
}
else
{

#if DataTracking
packCount = FullBuffer1;
FullBuffer1 = 0;
/********************************************************************/

if (packCount != 90)
{
CyU3PGpioSetValue(FX3_CTL10_OUT, 1);
lvCount++;
CyU3PGpioSetValue(FX3_CTL10_OUT, 0);
}

//packCountPerFrameOld = packCountPerFrame;
//packCountPerFrame = 0;
/********************************************************************/
#endif
/* A partially filled buffer indicates the end of the ongoing video frame. */
CyFxUVCAddHeader (dmaBuffer.buffer - CY_FX_UVC_MAX_HEADER, CY_FX_UVC_HEADER_EOF);
}

/* Commit Buffer to USB*/
status = CyU3PDmaMultiChannelCommitBuffer (chHandle, (dmaBuffer.count + CY_FX_UVC_MAX_HEADER), 0);
//status = CyU3PDmaMultiChannelDiscardBuffer(chHandle);
if (status == CY_U3P_SUCCESS)
{
pobCount++;
}
else
{
dmaError = status;

// if(glDmaResetFlag == CY_FX_UVC_DMA_RESET_EVENT_NOT_ACTIVE)
// {
// glDmaResetFlag = CY_FX_UVC_DMA_RESET_COMMIT_BUFFER_FAILURE;
// CyU3PEventSet(&glFxUVCEvent, CY_FX_UVC_DMA_RESET_EVENT, CYU3P_EVENT_OR);
// }
// break;
}

/* Check if any more buffers are ready to go, and commit them here. */
status = CyU3PDmaMultiChannelGetBuffer (chHandle, &dmaBuffer, CYU3P_NO_WAIT);
if (status == 0)
{
repeaCout++;
}
}

CyU3PGpioSetValue(FX3_CTL50_OUT, 0);
}
else if (type == CY_U3P_DMA_CB_CONS_EVENT)
{
CyU3PGpioSetValue(FX3_CTL50_OUT, 1);

conCount++;

streamingStarted = CyTrue;
glCommitBufferFailureCount = 0; //Reset the counter after data is consumed by USB

CyU3PGpioSetValue(FX3_CTL50_OUT, 0);
}

CyU3PVicEnableInterrupts(InterData);
}

Here are the results of my monitoring：

• The numbers I've edited in the image indicate the number of caches available to me at the moment
• Wider pulses indicate that the producer socket has finished producing buffers, and shorter pulses indicate that the consumer socket has finished consuming them

I think the problem is where I drew the circle, the host did not come to read the data in time, resulting in my buffer all occupied, I can not receive new data through GPIF, so the frame data is incomplete

So I widened my LV signal and this phenomenon was alleviated, but it still occurs when I occupy a higher CPU or open other usb cameras.

I am using 4 buffers and the buffer size is 46,080 (1024*3*15), I can't increase the number of buffers anymore because there seems to be not enough memory. In this case, how can I ensure that the data is not lost and how can I make the host read the data in time?

QingBao

USB3 GEN1 Bus interface:  I’m using the CX3 in USB2.0 interface/mode only.  Questions:

1. Is there any concern about using CX3 in USB2.0 (480mbps) only?
2. How the USB3 signals ,SSRX+/- and SSTX+/-, should be terminated?  Floating all, or floating SS-TX and terminating SSRX with resistors?  Please detail.

Max power consumption: Please let me know max possible power consumption (current) for the following rails:

1. VDDIO = powered by 1.8V. max current?
2. VDDIO2 and VDDIO3 = powered by 3.3V. max current?
3. VDD-MIPI, VDD, AVDD, U3TXVDDQ, U3RXVDDQ = powered by 1.2V. max current?
4. CVDDQ = powered by 2.5V. max current?

Clocks:

1. CX3 REFCLK, pin F2, is driven by oscillator PN SIT1602BC-72-18E-19.200000 (25PPM).  Any concerns about using this oscillator?

2. CX3 CLKIN, pin D7, is driven by oscillator SIT1602BC-72-25E-19.200000 (25PPM). Any concerns?

3. CX3 CLKIN-32, pin D6, is tie to GND. We are not driving this clock.  Our application is not using the Watchdog Timer function, UART or I2S.  However,  the I2C and SPI communications are utilized. Any concerns about not driving CLKIN-32?

I updated the header file of the project from "fw_lib/1_3_3/inc" to "fw_lib/1_3_4/inc". An issue occurred where SPI cannot operate at high frequencies. SPI can only operate at transmission speeds below 4M, and data transmission errors will occur after exceeding 4M. I want to know the difference between these two versions? What should I modify to adapt to "fw_lib/1_3_4/inc"?

Do you provide any testing documentation that would be suitable for FDA submission of a product which utilizes the FX3 Core Library? If not, could that be generated in any way?

We are evaluating what would need to be done to verify the firmware for a medical product and currently the libraries would be classified as SOUP because there is no source code provided as far as I'm aware.

Hello community and Infineon experts.

I am attempting to use the FX3 with a parallel video stream coming from an FPGA.  Hardware used is the FX3 Explorer board and a Lattice EVK.

For a first try the FPGA output is a test pattern, with the video format matching the default values in the project.  The only change made is to bypass SensorInit()  and turn on debug options.

However, nothing can be seen in the UVC output, and from debug output it seems that no data is received by the FX3?  (see UART output below).

The connections made are PCLK ->  PCLK, LV -> CTL11, FV -> CTL12.  And D0 - D7 on DQ0 - DQ7.  Signals seem correct as measured with scope.

1) Are these connections correct, for the Explorer board? 

2) Is there any further diagnosis that can be done to check if data is received?  Or any other suggestions.

Thank you!

Application Started
UVC: Completed 0 frames and 0 buffers
Current state = 1
UVC: Completed 0 frames and 0 buffers
Current state = 1
UVC: Completed 0 frames and 0 buffers
Current state = 1
UVC: Completed 0 frames and 0 buffers
Current state = 1
UVC: Completed 0 frames and 0 buffers

Hello everyone, I'm using CYUSB3014 to read data from FPGA, with 32 data bus width、16K bytes of each buffer, 1024 bytes of endpoint packet size, and the watermark is 7. When I use the USB Control Center to read the buffer data, the problem is the data after 0x000000FF is 0x00000102, instead of the correct data 0x00000100. And the data after 0x000001FF is 0x00000206, instead of the correct data 0x00000200, and so on. Except the above phenomenon, the other data is correct. Thank you for all your help. 

Hello Team,

            I want to send data to Xilinx Artix FPGA via cypress cyusb3014 fx3 via UART in python or LabVIEW. Can anyone please support me with the same. Actually we are using HSDCPRO GUI .dll to communicate Cypress FX3 by flash>Ram>slavefifosync.img (texas instrument disk image file) and send the data to Xilinx Artix FPGA by using AFE5832LPTX EVM Texas instrument GUI. Currently i want to make the scripts in python or LabVIEW without calling HSDCPRO GUI .dll to communicate Cypress FX3 and send the data to Xilinx Artix FPGA. Please help me to figure out the issue.

Thanks

Hi

I am using Cypress usb bootloader device (vendor ID-0x04b4, product ID-0x00f3) then control center am flashing the slavefifosync(provided by Texas instruments for HSDCPRO GUI) disc image file via ram.once done those things, control center it turns like Texas instruments usb mhr bootloader (vendor ID-0x0451, product ID- 0xaefd).i want to send the registers to xilinx artix 7 FPGA via fx3. How i can send the register file to artix 7 FPGA & read the data from FPGA via fx3. Is there any slavefifo image file available with you to write and read the data from artix 7 FPGA or can you please provide the python or LabVIEW source file if it's available.I need to send data via usb to uart(serial interface) and read the data via GPIF(Parallel interface) is it possible?can you please help us...