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I am working on a project with UVC hardware. I am taking the analog video data from an ADC with an FPGA and send the pixel data to USB FX3 chip. ...
I am working on a project with UVC hardware. I am taking the analog video data from an ADC with an FPGA and send the pixel data to USB FX3 chip. I am using an FPGA board and the ADC board is seperate from this board, they are connected via connectors. LVDS outputs of ADC should be routed differentially on PCB, which is fine because i can do that since i design the ADC board. However, there is a problem, LVDS traces between the FPGA board connectors and FPGA chip should be routed differentially. I was previosly using the FPGA board of Ztex 2.14e, which includes an FPGA chip and Cypress FX3 chip, but this board's IO traces are not routed differentially.
So, here is my question, do you know any alternative FPGA boards which includes an FPGA chip and Cypress FX3 chip? Also, the USB chip should be programmable on this board since i need to use the FX3 chip with UVC hardware.
I have followed several threads regarding this topic. I see most of them end without clarification that "solutions "worked as there were follow up qu...
I have followed several threads regarding this topic. I see most of them end without clarification that "solutions "worked as there were follow up questions that were never answered.
I have a 1920x1200 sensor running at 45fps which I know surpasses the parallel pixel clk of 100 Mhz. I would like to pack the pixels to a 24bit image. As stated above, I have tried to follow a lot of the threads and tried many of the settings with no success. I'm looking for a little support, with using the EZ USB suite. Will it correct create the c files if setup they way I want (as above) or do I have to massage the settings once it creates them (i.e. frame size, image size, etc.?)
Can't open the third camera with error(No space left). while currently the bandwidth of one camera is about 8 * 2 * 1024 * (1000000 / 125) / (1024**2) = 125Mbps(bInterval=1, bMaxBurst=7, Mult=1), for two is 250Mbps, much less than 90%(from USB3.0 spec) of the 5000Mbps, why can't it allocate bandwidth for the third camera?
Hello, FX3 datasheet contains GPIF II timing diagram for asynchronous DDR mode. However, there is no any additional information about how to use th...
FX3 datasheet contains GPIF II timing diagram for asynchronous DDR mode. However, there is no any additional information about how to use this mode. It is also unclear how to configure this mode in GPIF II Designer.
The API has only one thing that has relation to DDR -- DDR_MODE flag in GPIF_CONFIG register. Documentation says DDR_MODE flag "Select 2X clock as the core clock". That's all.
My guess is that setting DDR_MODE and DLE_PRESENT will allow for latching of DQ lines on every (both rising and falling) edge of CTL.
Is my understanding correct? Could you please clarify.