USB Superspeed Peripherals

Hi,

We intend to use a camera module (sensor + FPGA) with the FX3 and UVC to the Host like in AN75779.
The module outputs VGA@60fps but has a pretty low pixel clock (20MHz).

I’m trying to check if the module timing is compatible with the GPIF state machine as described in AN75779.
I’m struggling to find information in the spec/appnote/community on the shortest horizontal and vertical blanking times or clock cycles required.

As far as I understand AN75779 GPIF state machine:

• The horizontal blanking must be at least 2 pixel clocks as everything happens within the GPIF state machine going through LINE_END_SCK0/1 state chains
• The vertical blanking must be much longer as it involves interrupt in the FX3 CPU and SW back triggering of the GPIF state machine (next to pixel clocks required to progress in the state machine).

Is my understanding correct ?
Is there a minimum time (for a given CPU clock) I can take in account for the vertical blanking?

Thanks in advance
JC

Hello,

For my project, I'm currently using the FX3 (CYUSB3014) and looked into the SPI GPIO bit banging example as reference for the bit banging approach and given my timing requirements, it seems that we would need a delay less than a microsecond in between bits. From the looks of it, the smallest delay that can be used is with the CyU3PBusyWait (1uS). Is it possible to sample the logic levels of the GPIO pin/s with smaller delays and perform bit banging at a faster rate?

Thanks

Hi

I am developing a firmware that streams data  at 1080p@30 fps, I have  attached the parameters given I am not able to do streaming , the project is also attached , Is there any wrong configuration setting.

Thanks in Advance

I'm feeling a little out of my depth here as I'm a System Administrator rather than a seasoned Electronics Engineer, I hope this question makes sense...

I am trying to upgrade two machines, that each have several Cypress Westbrige devices attached to them, from Ubuntu 16.04 to Ubuntu 20.04. With Ubuntu 16.04, all devices enumerate correctly first as 04b4:00f3 and then go on to download their custom firmware, detach and reattach. However, with 20.04 I get the following errors:

Feb 23 12:05:47 master kernel: usb 1-6-port1: status 0101, change 0000, 12 Mb/s
Feb 23 12:05:47 master kernel: usb 1-6-port1: indicator auto status 0
Feb 23 12:05:47 master kernel: usb 1-6.1: new full-speed USB device number 3 using xhci_hcd
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:47 master kernel: usb 1-6.1: new full-speed USB device number 4 using xhci_hcd
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:48 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:48 master kernel: usb 1-6-port1: attempt power cycle
Feb 23 12:05:48 master kernel: usb 1-6-port1: not enabled, trying reset again...
Feb 23 12:05:48 master kernel: usb 1-6.1: new full-speed USB device number 5 using xhci_hcd
Feb 23 12:05:48 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:48 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: device not accepting address 5, error -71
Feb 23 12:05:49 master kernel: usb 1-6.1: new full-speed USB device number 6 using xhci_hcd
Feb 23 12:05:49 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: device not accepting address 6, error -71
Feb 23 12:05:49 master kernel: usb 1-6-port1: unable to enumerate USB device

Two other similar devices connected to this machine at 1-6.3 and 1-6.4 show identical errors.

I have tried:

• using 'uhubctl' to power cycle the ports of the 1-6 hub
• using 'uhubctl' to reset each of the ports on the hub
• adding the 'usbcore.autosuspend=-1' kernel parameter (after reading your KBA222372 - Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration)
• adding extra time for the device descriptor read with kernel parameter 'usbcore.initial_descriptor_timeout=10000' (10s rather than the default 5s)
• setting various combinations of 'usbcore.use_both_schemes' and 'usbcore.old_scheme_first' to change method the kernel uses to initialise USB device

Have any other users experienced similar problems Cypress FX3 based devices when running Ubuntu 20.04?

Thx

Hi, 

I made my custom board(FX3 and Camera Module).

I connected it and wrote my custom source code.

The black screen was printed in AMCAP, so I checked the debug message with wireshark.

The Wireshark confirmed that the data was output.

The resolution is 340(W) x 260(H), 30fps and 12bit data output.

You can see data in wireshark log.

• wireshark log  => ((16380 * 10) + 13292=177,092     
• resolution  =>  340*260*2 = 176,800
• difference => 177,092 - 176,800 = 292
• As above, additional buffers are entered, and it is necessary to check if there is a problem with the code.

I tried to change DMA Buffer size(CY_FX_EP_BULK_VIDEO_PKT_SIZE and CY_FX_EP_BULK_VIDEO_PKTS_COUNT ) in uvc.h

If i change buffer size, the buffers in the data packet are output differently.

Regards,

Jay

你好，我使用一个uvc工具验证发送设置camera 图像对比度，饱和度命令，但是CyU3PUsbRegisterSetupCallback(CyCx3AppUSBSetupCB, CyTrue)注册的回调函数不响应，函数头里加了日志也没有通过串口打印出来。此uvc工具直接测试usb camera摄像头是有效果的。我想咨询一下，fx3需要如何注册回调函数才会响应类似命令？

Hi, there are two GPIF threads which are similar to AN75779's mechanism in my project, and it can transfer image data smoothly.
Now, I’m researching GPIFII’s "DMA ready" ability. Therefore,  I’ve TWO questions for that.

Q1: In the GPIFII - Interface Definition tab, I set the DMA flags: 2

And my flag setting

After this setting, the corresponding pin will output HIGH while the DMA thread X is ready, and output LOW while the DMA thread X is preparing?

Q2: If I just want to use "DMA ready" ability, I can use FW api - CyU3PGpifOutputConfigure() to TOTALLY REPLACE Q1’s GPIFII setting?

Why I ask that? Because I found if I programmed the code as

The "DMA ready" pins still output the signal, even though I DON'T set the Q1’s setting.

Any help will be highly appreciated!

Hi,

I want to transfer video data from FPGA to PC by using custom board  FX3- CYUSB2014. Output data from FPGA : 640x480, 30 fps, 90 MHz clock, YUY2 format, 8 bit data bus connected with  2.0 USB cable  to host PC. I edited AN75779 firmware but without success. I use VLC, USBVideoClassBulk works fine on my hardware. Is there anything am missing to change?

Tom

In  cyfxuvcdsr.c file

/* Standard High Speed Configuration Descriptor */

/* Class specific Uncompressed VS Frame descriptor */

        0x1E,                           /* Descriptor size */

        0x24,                           /* Descriptor type*/

        0x05,                           /* Subtype: uncompressed frame I/F */

        0x01,                           /* Frame Descriptor Index */

        0x01,                           /* Still image capture method 1 supported */

        0x80,0x02,             //z         /* Width in pixel: 640 VGA */

        0xE0,0x01,             //z         /* Height in pixel 480 VGA */

        0x00,0x00,0xCA,0x08,   //z         /* Min bit rate bits/s. 640x480x30x16

        0x00,0x00,0xCA,0x08,    //z        /* Max bit rate bits/s. Not specified, taken from MJPEG */

        0x00,0x60,0x09,0x00,    //z        /* Maximum video or still frame size in bytes(Deprecated) */

        0x15,0x16,0x05,0x00,      //z      /* Default Frame Interval 30 fps*/

        0x01,                           /* Frame interval(Frame Rate) types: Only one frame interval supported */

in uvc.c file

uint8_t glProbeCtrl20[CY_FX_UVC_MAX_PROBE_SETTING] = {

    0x00, 0x00,                 /* bmHint : no hit */

    0x01,                       /* Use 1st Video format index */

    0x01,                       /* Use 1st Video frame index */

    0x15,0x16,0x05,0x00, //z     /* Desired frame interval in the unit of 100ns: 30 fps */

    0x00, 0x00,                 /* Key frame rate in key frame/video frame units: only applicable

                                   to video streaming with adjustable compression parameters */

    0x00, 0x00,                 /* PFrame rate in PFrame / key frame units: only applicable to

                                   video streaming with adjustable compression parameters */

    0x00, 0x00,                 /* Compression quality control: only applicable to video streaming

                                   with adjustable compression parameters */

    0x00, 0x00,                 /* Window size for average bit rate: only applicable to video

                                   streaming with adjustable compression parameters */

    0x00, 0x00,                 /* Internal video streaming i/f latency in ms */

    0x00,0x60,0x09,0x00,   //z  /* Max video frame size in bytes */

    0x00, 0x40, 0x00, 0x00,      /* No. of bytes device can rx in single payload = 16 KB */

0x00,0x00,0x00,0x96,                 /* Max video frame size in bytes */

/* Configure the IO matrix for the device. */

    io_cfg.isDQ32Bit        = CyFalse;