USB superspeed peripherals Forum Discussions

In my custom design. A FPGA transfers video stream data though gpif port and  a FX3 chip transfers it to PC .

But PC doesn't get data continuously , data read stops at 4~8 times transfer for  8192 byte data. (burst mode).

In stop state, DMA Full flags are all full .  If  try data read again , it also stops at at 4~8 times transfer again.

in pc side ,  5ms Sleep Function between transfers  disappears the stop situation ( data loss ).

in pc side , I use XferData( buf , 8192)  repeatly . 

in FX , gpif sync_slave_fifo_2bit ,  Multi-channel Dma auto mode  using thread 0 and 1.

Hello I've been using a modified slave fifo configuration based on the AN65974 application note. A Xilinx development board is connected to the FX3 SuperSpeed Explorer Kit which is then connected to a PC. We've successfully used this set up to transfer a frame's worth of imaging data for a custom ultrasound system (128KB of data per frame). Recently we've upgraded the imaging system to double the pixel density. Now for each frame we need to send 256kB of data to the PC. This is where we've been having more interesting results. When requesting 256KB using xferdata() the first 128KB correspond to the second half of the previous frame, and the second half of the data corresponds to the first half of the current frame. I've run integrated logic analyzers (ILAs) on the FPGA to ensure that the data being written to the FX3 is in fact correct, so I am certain that the problem does not lie in the writing or reading of data from the FPGA. I should also state that once the frame data is sent to the FX3 chip, the memory is cleared and thus cannot be repeated on the next acquisition. A small fix that I've attempted to implement (with moderate success) was to request a frame and a half of data (384KB). I would throw away the first 128KB and subsequently plot the remaining 256KB. This method unfortunately is not ideal for obvious reasons, but I also seem to be losing a small amount of data using this method and it manifests into a imaging artifact propagating through each image. I've also tried performing 16 sequential xferdata() calls for 16KB of data which did not sort out the problem. I've also replicated this error on our previous platform requiring on 128KB worth of data by forcing the PC to request double the amount of data from the FPGA. Since the circular buffer inside the DMA has 8x16KB = 128KB, I'm suspicious that the root cause has to do with the manner of which we're requesting data from the FX3. We've kept it relatively simple using the xferdata() function.

I'm hoping someone can give me some insight as to why the FX3 chip seems to be storing the last 128KB of data that I've transferred on the previous xferdata() request. Some insight would be greatly appreciated. Thanks in advance.

 I have made a fx3 PCB.when I download a program by USB2.0 interface, The computer can recognize the board.

 But when I download by USB3.0 interface, the Control Center show "programed successfully", but the Control Center can not recognize the board any more.I think maybe the driver causes the problem. But I can not find any device like the board in my device manager and the computer has been install intel USB3.0 driver. 

 Who ever have met the problem,I think I need some help.

Best Regards.

Lin

Hi Everyone,
 

We are using RAID-on-Chip reference board that has FX3S controller. We are successfully able to use default "Bulk Streamer" firmware with default "C++ Streamer" host application over USB 2.0 interface.

When we try same firmware and connected the board with USB 3.0 ports it does not appear in device manager. After trying with different USB 3.0 host controllers it sometimes appears on one single port only (Intel (R) USB 3.0 eXtensible Host Controller, Driver version 2.5.0.19).

It enumerates as USB 3.0 device, which we verified using "USB Control Center application" and another third party USBview application. However, the C++ Streamer application fails with error code : 0xc000000d. Also, "USB Control center" application does not seem to transfer anything over both (IN and OUT) endpoints. Error code: 997.

Do we need to change default firmware or default application to use USB 3.0 functionality of cypress FX3S controller ?

If not, then can anyone suggest what might be the issue ?

This is really urgent so any help would really be appreciated.

Thank you in advance.

Hi,i use the c# project  of control center ,and i do not change anything,but when i debug,it can not generate successfully.

Hi,

I am thinking of using FX3 as a host.

But "AN77960 - Introduction to EZ-USB® FX3™ High-Speed USB Host Controller" is now obsolete.
Any reasons why it is obsolete? Is it impossible to use FX3 as a host?

Regards,

Hi,i am doing a projec to use the GPIF II interface as the master to write and read from  a SRAM.I have tested that i can write and read successfully use a few byte,but i want to know how can i to write and read a few million byte.Iwant to know how to set the DMA and others which is related with my aims.And the GPIF II project whether should be changed for this.

Thanks.

Hi all,

what is the more reliable method to detect when the host has granted the FX3 device the power it has requested by its descriptors (either in USB2.0 and USB3.0)?

I'm searching a good place to put the peripheral initialization of my board...

Thanks a lot!

Hi all,

CyU3PUsbSendEp0Data has a race condition that can cause delays of 500ms per call, despite successful completion. I just wanted to discuss a work-around or a fix.

Scenario:

    
1. implement a control IN transfer that spans multiple USB Control Endpoint packets (e.g. 2048kB)
    
2. the firmware shall respond in chunks of MaxPacketSize (e.g. USB-3.0 super-speed connection: 512 Bytes; else 64 Bytes)
   

As per SDK API documentation of CyU3PUsbSendEp0Data(), this is an acceptable implementation: cyu3usb.h states "Multiple calls of this function can be made to respond to a single control request as long as each call sends an integral number of full packets to the host."

Recently, we noticed that this sometimes leads to long-lasting transfers, that often even hit the time-out of the host applications DeviceIoControl calls. For example, it happens using a Intel(R) 6 Series/C200 USB Enhanced Host Controller (USB-2.0 high-speed).

A work-around seems to be increasing chunk size, i.e. using 512 Bytes per call even for USB-2 connections. But how can I know, how much margin it provides?

The problem can be traced down to a race condition. In CyU3PUsbSendEp0Data(), after CyU3PDmaChannelSendData the DMA socket state and Egress Endpoint Manager state are checked (with time-out of 500ms):

        while ((((UIB->sck[0].status & CY_U3P_UIB_STATE_MASK) >> CY_U3P_UIB_STATE_POS) != CY_U3P_UIB_STATE_ACTIVE) ||                 ((UIB->eepm_endpoint[0] & CY_U3P_UIB_EEPM_EP_READY) == 0))

Please find attached a modified version of the source code. It reports these status signals before and after the while-loop.

It can happen that socket state is already CY_U3P_UIB_STATE_STALL and the EEPM is not ready. This can be enforced by adding a small delay before "while" (also contained in the attached source file). This condition seems to tell that the transfer has already completed.

Obviously, the while-loop can be improved. My proposed solution would be adding the following lines to the loop body:

    if ((((UIB->sck[0].status & CY_U3P_UIB_STATE_MASK) >> CY_U3P_UIB_STATE_POS) == CY_U3P_UIB_STATE_STALL)         && ((UIB->eepm_endpoint[0] & CY_U3P_UIB_EEPM_EP_READY) == 0))         break;

But is this safe? I maybe do not completely understand the meaning and side-effects of these flags.

Thanks

Hi,

I tried, run in administrator, the command:

>regsvr32 Cyusb.dll

and got the error : cyusb.dll was loaded, but the Dllregisterserver entry point was not found.

How can I install the cyusb.dll or cyapi.lib ?  

Thanks.