USB superspeed peripherals Forum Discussions

Happy new year to you all,

I just wanted to ask if we can plug directly the GPIO of the EZ USB FX3 to an FPGA Type Altera Cyclone IV without using a HSMC interconnect board ( just connect directly the pins ) and would that affect the transfer rate ?

Thank you in advance for your help 

Greetings.

This is a really good application note for GPIF => USB integration but is sadly lacking the GPIF design files. Can anyone provide them? 

TAIA.

Jerry

We're using a Cypress FX3 GPIF II Slave FIFO interface in a many-to-one configuration driven by a custom FPGA.  We have noticed an issue that we cannot explain.

Our FPGA is running on a continuous 112MHz sampling clock generating 16kB frames of data.  We are using two ping-pong buffers 4 deep for both channels feeding the socket.  Every such frame, the FPGA updates a unique 16 bit ID that is placed in the frame to allow us to ensure data integrity - we need to avoid gaps.  During normal operation, the system works just fine.  The initial startup is the problem - the very first time we cycle back to the front of the DMA buffer ring (that is, after the eight frame), we see a gap in the data.  Our frame IDs run through a sequence 0, 1, 2, 3, 4, 5, 6, 7, 77, 78.....

We start and stop the FPGA when starting and stopping data acquisition frequently during normal operation, which also pauses the Slave FIFO interface.  Upon restart, there is no such gap in the data.  It happens only on the very first startup of the channel.  Another product uses a similar system but a different DMA buffer count, and it too sees the exact same wrap around problem once and only once every power cycle.  Let me add that the actual channel creation and state machine startup happens much earlier than the first acquisition, so we believe the system to be fully up and running when this happens.  

So it seems that there is a 1-time delay associated with wrapping the GPIF II engine back around to the front of the DMA buffer queue.  Is this expected?  

hello,

 Visual studio based gui has been given for DMA access of data. Can you provide GUI based example for controlling the user I/Os of usb 3.0 FX3 Superspeed kit using PC.

thanks

Hi, dear friends,

    I met a problem in FX3 to receive residual data in FX3: in order to achieve high speed, I set a large transfer data length for XferData() function, such as 1024*128, but at the end of the data transfer, there will be a little amount of data smaller than 1024*128. So when XferData() time out and meet error, I call XferData()again and try a smaller data length , but It's will never succeed and can't receive the data tail . But if I set a smaller data length all the time, I can receive the tail.

    Does anybody know how to solve this problem? Thank you very much and best wishes.

Hi, I have a design that requires an FPGA and a CPLD, each connected to the FX3. The FPGA is to be connected to the FX3 using the FIFO interface, with the FX3 as the FIFO slave. The CPLD, on the other hand, is to act as a slave to the FX3, and needs to transfer data relatively quickly, so the GPIOs are not sufficient.

This was accomplished on the FX2LP by connecting the FPGA to the Slave FIFO interface of the FX2LP and connecting the CPLD to the Address and Data lines of the FX2LP. I am looking to port this design over to the FX3, but by using the GPIF II as a Slave FIFO, I am not sure how to then hook up the CPLD as a slave device to the FX3, due to pin constraints and the fact that using the FIFO requires the GPIF.

Part of the schematic from the FX2LP version is attached for a visual aid. J3 connects to the FPGA and U7 is the CPLD.

Thanks!

Hello, may be you can help me

I use CYUSB3014 with FPGA bus 32 bits, 50 MHz, don't work correct Bulk In EndPoint.

All work good if i commit data buffer used PktEnd signal with 1-255 DWORDs (4 - 1020 byte). But if i use PktEnd signal for more data, USB Monitor write me USB device 'Surprisingly removed'.

If i don't use PktEnd signal USB device send data only than packed buffer full, each pack 16384 bytes, but if buffer not full does not send data.

Hi!

Our board, after power on has VIO1-VIO3 domains turned off. What about peripheral configuration at this domains? In most cases it returns without errors, but in which state this peripheral will be after power up?

Mostly interesting for the GPIO. We use GPIO[57] at the domain VIO4 to turn on all other blocks (commutate power driver). To operate with GPIO we must configure it and configure pins. Pins configuration for the powered down domains (GPIO[27] for example) passes without error. Is it configuration will be valid after power up?

Or Should I do next steps:

1. Init GPIO

2. Configure only POWER pin

3. Enable POWER

4. Wait

5. Configure other pins and other peripheral

?

PS also with powered down domains VIO1-VIO3 chips detects as CYPART_WB0263, is it correct?

 I wrapped some cyapi.lib functions for my python project. I am using MinGW(3.4.5) to compile and link my files.

But I always get g++ error as follows. Compiling of .cpp and .c files is successful. But it never succeed to link to cyapi.lib. I include all libs that I can think of, like setupapi.lib, user32.lib, kernel32.lib, etc.  I am sure cyapi.lib is accessible to my g++ compiler, and I am sure g++ accessed cyapi.lib, but somehow g++ cann't resolve the definition in cyapi.lib. 

No matter I use gcc.exe or g++.exe to compile wrapcyapi.cpp, the error stays. 

My question is: is cyapi.lib readable to gcc? What should I do? 

C:\MinGW\bin\gcc.exe -mno-cygwin -mdll -O -Wall -Ic:\python27\include -Ic:\pytho
n27\PC -c wrapcyapi.cpp -o build\temp.win32-2.7\Release\wrapcyapi.o
C:\MinGW\bin\gcc.exe -mno-cygwin -mdll -O -Wall -Ic:\python27\include -Ic:\pytho
n27\PC -c extension.c -o build\temp.win32-2.7\Release\extension.o
writing build\temp.win32-2.7\Release\winusbext.def
C:\MinGW\bin\g++.exe -mno-cygwin -shared -s build\temp.win32-2.7\Release\wrapcyapi.o build\temp.win32-2.7\Release\extension.o build\temp.win32-2.7\Release\winusbext.def -L./lib/x86 "-LC:/Program Files/Microsoft SDKs/Windows/v6.0A/Lib" -Lc:\python27\libs -Lc:\python27\PCbuild -lCyAPI -lSetupAPI -lUser32 -lKernel32 -lgdi32 -lwinspool -lcomdlg32 -lpython27 -lmsvcr90 -o build\lib.win32-2.7\winusbext.pyd
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x95):wrapcyapi.cpp: undefined re
ference to `CCyUSBDevice::GetDeviceDescriptor(_USB_DEVICE_DESCRIPTOR*)'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0xef):wrapcyapi.cpp: undefined re
ference to `CCyUSBDevice::~CCyUSBDevice()'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x178):wrapcyapi.cpp: undefined r
eference to `CCyUSBDevice::CCyUSBDevice(void*, _GUID, int)'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x1b7):wrapcyapi.cpp: undefined r
eference to `CCyUSBDevice::EndPointCount()'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x29d):wrapcyapi.cpp: undefined r
eference to `CCyUSBDevice::~CCyUSBDevice()'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x31e):wrapcyapi.cpp: undefined r
eference to `CCyUSBDevice::CCyUSBDevice(void*, _GUID, int)'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x35d):wrapcyapi.cpp: undefined r
eference to `CCyUSBDevice::EndPointCount()'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x3f6):wrapcyapi.cpp: undefined r
eference to `CCyUSBDevice::Open(unsigned char)'
build\temp.win32-2.7\Release\wrapcyapi.o(.text+0x41d):wrapcyapi.cpp: undefined r
eference to `CCyUSBDevice::DeviceCount()'

eference to `CCyUSBDevice::Close()'
collect2: ld returned 1 exit status
error: command 'g++' failed with exit status 1

I tried some replies in the forum, but no lucky.

Thanks in advance for any reply.