USB superspeed peripherals Forum Discussions

Hello

Thank you for taking the time to answer this question.

Looking at using the CYUSB3013-BZXC part.  I think we only need the 16bit GPIF interface as the application is backward compatibly with the FX2, CY7C68013A-128 part and used the 16bit Slave FIFO Interface.  So we want to follow along that part when we migrate upto the new FX3 part.  Looking at the datasheet Table 20 shows the 5 different variants of the FX2, USB3011, USB3012, USB3013, USB3014 and USB2014.  Since we only need the 16 bit GPIF interface and we want the larger RAM I was planning on going with the USB3013 part.

Now going through the datasheet I see the Table 7 pinout for the USB3012 and USB3014.  But there is no pinout shown for the USB3011 and USB3013.  Do I infer this pinout from the subsections in Table 7 under 32 bit Data Bus/16bit Data Bus+UART+SPI+I2S/16bit Data Bus+UART+GPIO/16bit Data Bus+SPI+GPIO/16bit Data Bus+I2S+GPIO/GPIO only ???  Not sure if I am missing a table that I need for the USB3013 device or am I just missing something altogether.  

Note it looked like in revision L of the data sheet there was a table added for USB3011 and USB3013 pinout but then it was removed in revision Q.

Thank you for any help you can provide.

Gary

we  are designed usb sd3 based custom board. we have ported example illustrates the use of the FX3S firmware APIs to implement mass storage class device that allows access to SD/MMC devices connected to SD3 given along with SDK.

The application partitions the storage device found on storage port into two volumes, and then enumerates them as separate logical units on the USB side
in that example partitions  define by

#define CY_FX_SIB_PARTITIONS (2).

.If i have increased to 4 ,it shows 4 partitions .  Out of 4 partitions only two partitions data copying possible. If i have clicking other two partitions an message displays " please insert the disk".

kindly suggest how to make multiple partitions and also please tell how  to control partions size of eacj partion

I'm having some confusion about how the FX3 assigns the address pins based on the configuration file generated using the GPIF II Designer tool. I am using the SuperSpeed explorer kit and I would like to have a master interface with a 9-bit address bus; the designer tool shows me that the following GPIOs are assigned to the  address bus:

GPIO[46:49], GPIO[29:25]

I have the state machine trying to drive the address bus using DR_ADDR, which is reading from Register (not socket). In the firmware I have a loop that increments a variable, i, from 0 to 4 and I am writing this value to the register using CY_U3P_PIB_GPIF_EGRESS_ADDRESS(0) = &i

I have probed the GPIOs assigned by the designer, but I see no change in the output.

When I look in the FX3 technical reference manual there is a comment for the ADR_CTRL bit field in the GPIF_BUS_CONFIG register that says the following:

"Number of control lines overridden by address lines. Control signals CTRL[15] to CTRL[16-
ADR_CTRL] are not connected to pins. Instead those pins are designated as address signals. Which
address signals depends on the other mode fields above. In other words: if ADR_CTRL = 0 all CTRL
lines are connected to pins, if ADR_CTRL = 1, CTRL[15] is not connected and so on."

However the datasheet does not specify any pins that have the name CTRL[14] or CTRL[13] (see Table 7 for CYUSB1304) and this comment does not agree with the GPIOs assigned by the Designer tool. 

I am going to try and test the address bus output by driving using counter, just to make sure I am not having a board issue, but any clarification on the above would be appreciated.

Has anyone gotten CyU3PDeviceInit to work with a parameter other than NULL?

The PCB has a 19.2 MHz oscillator and does not have the 32.768 kHz crystal.

With CyU3PDeviceInit(NULL), our device boots. But the defaults seem to be different than those described in the API Guide.

The API Guide says the defaults should be: CPU divider = 2, DMA divider = 2, MMIO divider = 2, setSysClk400 = CyFalse, useStandbyClk
= CyTrue. And that this would run the GPIF at 96 MHz. but we measure 100.8 MHz.

Additionally, if we try to initialize with these defaults:

    clk_cfg.setSysClk400  = CyFalse;
    clk_cfg.useStandbyClk = CyTrue;
    clk_cfg.cpuClkDiv     = 2;
    clk_cfg.dmaClkDiv     = 2;
    clk_cfg.mmioClkDiv    = 2;
    status = CyU3PDeviceInit(&clk_cfg);

The device will NOT boot.

Are we missing something here?

Does sd3-CYUSB3023 supports in system programming? Does the FX-3 SDK provides full support for the CYUSB3023 mcu??

we  are designed usb sd3 based custom board. we have ported example illustrates the use of the FX3S firmware APIs to implement mass storage class device that allows access to SD/MMC devices connected to SD3 given along wit SDK.

The application partitions the storage device found on storage port into two volumes, and then enumerates them as separate logical units on the USB side
in that example partitions  define by

#define CY_FX_SIB_PARTITIONS (2).

.If i have increased to 4 ,it shows 4 partitions .  Out of 4 partitions only two partitions data copying possible. If i have clicking other two partitions an message displays " please insert the disk".

kindly suggest how to make multiple partitions.And i need to know how to make on partitions as readable partitions.

Hi,

I want to read 32 bits at a time using SPI.  I'm using a GPIO pin (simple configuration) as the interrupt signal to indicate when the data is ready to be read.  And using SPI register mode to read (based on the UsbSpiRegMode example).  There is about a 800 micro-second delay between the GPIO interrupt end edge and the SPI SSN signal start edge.  This delay is too long; it needs to be about 5 micro-seconds.  Is this long delay because I'm using a register read instead of dma read?  The actual read (SSN signal width) is ok -- about 3 micro-seconds.  Does register read have some setup lag?

    // Configure GPIO 34 as input INT_n
    // interrupt line activated when profile sensor data is ready, triggered by Start_n
    gpioConfig.outValue = CyTrue;
    gpioConfig.inputEn = CyTrue;
    gpioConfig.driveLowEn = CyFalse;
    gpioConfig.driveHighEn = CyFalse;
    gpioConfig.intrMode = CY_U3P_GPIO_INTR_NEG_EDGE;
    status = CyU3PGpioSetSimpleConfig(GPIO_INT_N, &gpioConfig);

Thanks.