Background: I'm designing an interface where I paired an FPGA with the FX3. I opted to use the "Synchronous Slave FIFO Interface" to interface with the FPGA. The FPGA is paired with 512MB buffer memory. The FPGA should only send streaming (bulk) to the host PC (using USB3/FX3).
The "Synchronous Slave FIFO Interface" has 2 bit addressing mode by default. But I have 2 questions about this:
1) Is there a drawback/advantage in not using any addressing at all? It seems to me it would make the design simpler.
2) Can I change existing the GPIF-II design (sync_slave_fifo_2bit) and remove the addressbus? I see no way to do this, since there are only a few options under "Interface Customizations" in de GPIF-II Designer which don't include any settings for the addressbus, like when starting from scratch. If I start from scratch I see no way of copying the statemachine from the Slave FIFO Synchronous", so that also seems rather cumbersome.
Any advice is highly appreciated.
I'm trying to stream 1080P MIPI Raw 10 image sensor . I if configure the MIPI transmitter section and receiver section for 1080p 30 Fps There is no problem in receiver side and It streams correctly. When I done this for 60 FPS I cant change the the output pixel clock in receiver configuration and it shows minimum is 129 and maximum is 100 even if my output video format size is 24-bit.
my camera can support 8/10/20 bit raw output of Bayer format and both continues and gated MIPI clock mode.
Kindly suggest me some settings for 1080P 60 fps.
I am using a CYUSB3014 as a synchronous slave fifo interface to an Altera FPGA master.
I have modified the 2-bit slave fifo sync firmware (attached) by adding two endpoints and I'm using it to transfer data at an expected rate of about 80 MB/s. The FX3 should handle this without breaking a sweat, but instead I am getting a lot of dropped data.
I am probing the related DMA_Ready flag with Signal Tap in Quartus. I see that it goes low at some point during the transfer and stays so that for such a long time that I can't even seethe end of it within the Signal Tap time range. I have implemented a fifo in the FPGA as a buffer, but it's not enough.
Any help towards solving this issue would be really appreciated. Thanks in advance.Show Less
I'm trying to stream MIPIraw 10 1920X1080 60fps in CX3 Denebola kit, When I tried to tried to stream camera in Linux host I got CB failure. Kind suggest some solutions to resolve this problem .
I am thinking about ways to verify that data is acquired continuously and for the host to recover in the event of a fault due to excess CPU load, USB glitch, etc. In this case I would like the host to know this has happened, throw out the data after the overflow, and signal to the FX3 to reset to just before the overflow.
One simple method I tried was to run in CY_U3P_DMA_TYPE_MANUAL_MANY_TO_ONE mode and then count CY_U3P_DMA_CB_PROD_EVENT events. I then append the current event count to each buffer and the host checks that the buffers are incremented with no gaps. However, in testing where I deliberately cause CYU3P_PIB_ERR_THRX_WR_OVERRUN events by overloading the USB host (PC) CPU, the received buffers always have continuous CY_U3P_DMA_CB_PROD_EVENT counts even though some data is lost to overrun and the CYU3P_PIB_ERR_THRX_WR_OVERRUN event is generated.
1) I had thought that the DMA engine would always cause a PROD event when I switch threads, but if the host doesn't drain the buffer fast enough, some of this data would be overwritten after causing the event. This does not seem to be the case, so when is the PROD event actually raised? How does an overrun happen without generating the PROD event?
2) Aside from counting PROD events, is there some other thing I can count in order to figure out if any DMA buffers are lost or overrun? If I understand correctly, there is no way for the CPU to access the current value of any of the DATA/ADDR/CTRL counters, but maybe there is something else that increments when the DMA engine switches threads? I think I could count CYU3P_PIB_ERR_THRX_WR_OVERRUN events, but it isn't clear to me how that timing on those works.Show Less
Through different questions already asked on your website, we have been able to solve majority of our issues.
However, for the custom we are currently developing, we cannot have the USB3.0 interface working.
We would like to solve this issue in the next iteration of our custom board by understanding what is preventing us from using the USB3.0 interface on this very design.
To avoid you some extra questions, I have resumed most of the things we developed, tested and probed.
As a potential important point, the onboard clock is 19.2MHz and not 24MHz.
I'm absolutely available if you need any more info or if you want me to test something else.
My colleague @cam will also follow this topic and answer your potential questions.
I am currently working on getting a new camera working on the same Cypress CX3 chip. We have created a very similar board to the one we have been using for the IMX241 with changes only to the LED illumination system and the camera connection to accommodate the larger packaged sensor, the IMX412.
This IMX412 is a 4056x3050 sensor. I have set this sensor up to output its central 5MP at 2592x1944 to match our previous camera’s setup. This streams at 43.4 fps with the current settings I have in place.
My current issue is that the device tends to reset quite often. And by reset I mean the following (from UART output):
EVENTFLAG Timer Reset Event, IsCameraSupposedtoBeRunning: 1, FrameIndexToSet: 2, FrameIndex: 2
This occurs just about 95% of the time within 60 seconds of streaming. My goal is to understand and mitigate this response as best as possible.
My understanding is that this occurs when the host has not pulled the data in the expected amount of time before the device is ready to output its’ next image. I am currently using Direct Show for my image capture. This is set up through a callback method and not doing any processing what-so-ever and just pulling the images into my program and releasing them after confirming a viable image in order to output FPS values.
My current Descriptor Settings:
My Hard set values:
My CX3 Clock:
My Camera Clock:
Camera Lines: **I have not been able to effectively reduce the Total pixels per line without causing a “step response” seen below the values.** Different problem but need to solve after this. Will only get us a max of 3 more fps since the device cannot handle more than 47 fps from this camera.
Please let me know if I can provide any more additional preliminary information to aid your understanding of this current issue. Thank you for your time.Show Less
We have a FX3 device which uses GPIF to keep reading large datasets from FPGA and then sends them to PC host through a bulk-in end point.
With Wireshark, we find that sometimes PC sends a clear-feature to the device to reset the bulk-in end point (before this, a bulk-in reading failure occurred on PC site). We think this maybe caused by some bulk-in transaction failures ( CRC errors , time-out, or USB device stalled, etc.) detected by PC host.
From the examples provided by Cypress, after receiving a clear-feature request, FX3 needs to reset the DMA channel associated with the bulk-in end point, flush and reset the end point, etc. . this may lead to the un-transmitted data lost in the DMA buffer.
Is it possible to retransmit the lost data after communication recovery (with GPIF interface between FX3 and FPGA, it is hard to do the data backup before transmission)? if so, how to do it?