USB superspeed peripherals Forum Discussions

Hi,

I need to implement a UVC-based application. There is a FPGA before the CYUSB3014. 

I find the video get stuck very often(every 2 or 3 minutes) on the AMCap. But after I restart the AMCap, the video could continue again.

And I find when the video stops displaying, the uart frame count also stops increasing but the video continues streaming from FPGA to USB.

What could the problem be? And what can I do (with the FPGA part or the USB firmware) to fix this issue?

P.S. I find the problem is "backflow detected...", has anyone met this before? 

P.P.S.  I have the same problem with the post below, do I need to create a case for technical support?

http://www.cypress.com/forum/usb-30-super-speed/an75779-not-stable-all?source=search&keywords=backflow&cat=community

Best Regards!

Hi,

    I have a CYUSB3014 board without EEPROM and SPI-FLASH, so that I need load firmware when board is power on every time. Can CYUSB3014 load firmware to inner ROM or inner Flash ?  And how could I do it?   Thank you very much!

best regards,

Tomsen

Hi,

I find CYUSB3014 IO configuration very complicated and confusing. My firmware is stored in a Flash memory and I choose the SPI boot option. Meanwhile I use UART for logging. UART_TX and UART_RX are configured to GPIO[55] and GPIO[56] which are also SPI_MISO and SPI_MOSI. Thus, only when I unplug the UART-USB converter from the PC host can the firmware be booted from the SPI flash.

Here below is my configuration.

    /* Configure the IO matrix for the device. */

    io_cfg.isDQ32Bit        = CyFalse;
    io_cfg.lppMode          = CY_U3P_IO_MATRIX_LPP_UART_ONLY;
    io_cfg.gpioSimpleEn[0]  = 0;
    io_cfg.gpioSimpleEn[1]  = 0;
    io_cfg.gpioComplexEn[0] = 0;
    io_cfg.gpioComplexEn[1] = 0;
    io_cfg.useUart          = CyTrue;    /* Uart is enabled for logging. */
    io_cfg.useI2C           = CyTrue;   /* I2C is used for communication with FPGA. */
    io_cfg.useI2S           = CyFalse;
    io_cfg.useSpi           = CyFalse;   // SPI Flash

I find GPIO[48] and GPIO[49] can also be configured to UART bus. How can I configure the IO matrix to avoid the multi-usage of GPIO[55] and GPIO[56]? 

Best regards!

Hi,

I would like to use UART, but configure UART_RT S and UART_CT S as GPIO pins and only use UART_TX and UART_RX for my UART communication.  Is this configuration possible?

When I try to configure the io matrix using the settings below, the firmware won't load.

    CyU3PMemSet ((uint8_t *)&io_cfg, 0, sizeof(io_cfg));
    io_cfg.isDQ32Bit = CyFalse;
    io_cfg.s0Mode = CY_U3P_SPORT_INACTIVE;
    io_cfg.s1Mode = CY_U3P_SPORT_INACTIVE;
    io_cfg.useUart   = CyTrue;
    io_cfg.useI2C    = CyFalse;
    io_cfg.useI2S    = CyFalse;
    io_cfg.useSpi    = CyTrue;
    io_cfg.lppMode   = CY_U3P_IO_MATRIX_LPP_DEFAULT;

    io_cfg.gpioSimpleEn[0]  = 0x0;
    io_cfg.gpioSimpleEn[1]  = 0x4000; // GPIO46 as simple
    io_cfg.gpioComplexEn[0] = 0x0;
    io_cfg.gpioComplexEn[1] = 0x8000; // GPIO47 as complex

Thanks.

Hello all!
I'm novice here and I try to make composite device.
So, I have a project CDC_BulkLoop_composite.zip (based on original CDC_BulkLoop project). Changing PID I can view two devices on Windows'7x64: 1 COM-port (it seems which works correctly) and 2) Unknown Device. Win'7 can not find driver for 'Unknown Device'. 
So, my question is: 
What I need modify or change to work with second 'Unknown Device' in 'CyControl' software ( INF-file, fx3-project sources, anything else)? Or can I do myself driver (based on KernelDriver or WinDriver) to work with 2'th device. What way is shorter and good for me?

Thanks in advance for any response!
Regards, 
Evgeniy

P.S.: Now second unknown device is a original CDC-device (not a slave-FIFO device). It will be slave-fifo in future. 'CyControl' software is good for me. I want to use it. But if it is impossible, I can write myself program. 

An errors will occur when I send a USB VENDOR_REQUEST from PC

#define CY_FX_THREAD_STACK       (0x4000)                   /* Master application thread stack size */
#define CY_FX_THREAD_PRIORITY    (8)
------------------------------------------------------------------------------
uint8_t Ep0Buffer[4096] __attribute__ ((aligned (32)));//4KB max
uint8_t buffer1[64];
------------------------------------------------------------------------------
case VENDOR_REQUEST_1:
    return_state = CyU3PUsbGetEP0Data(DATA_FRAME_LENGTH, Ep0Buffer, NULL)
    function1(64, Ep0Buffer, buffer1);
break;
------------------------------------------------------------------------------
_tx_thread_stack_error_handler() at 0x40024088
_tx_thread_system_suspend() at 0x4001e628    

_tx_thread_sleep() at 0x4001e55c    

CyU3PUsbHandleEvents() at 0x4001b454    

CyU3PUibThreadEntry() at 0x4001a74c    
_tx_thread_shell_entry() at 0x40023f1c    
0x0 

------------------------------------------------------------------------------
Please Help

Thanks

Hi，

  I'm trying to run the example of Slave FIFO in BulkLoop Mode ,but use our Altera FPGA Board. I have some problems with the FlagA & FlagB. Here I set the FlagA & FlagB as Full-Flag and Amost-Full-Flag of Thread_0 which is getting data from FPGA and sending to PC.  Here my Fifo databus is 16bit , the watermark of Thread_0 is 6 and the watermark of Thread_3 is 2.

Here is my problems:

 1.  I find the FlagA & FlagB both high in initial state When I send a text File Out(size 512) through the Control Center. Is that right?

2.  Through the waves, I find the FlagA & FlagB doesn't change when Status Machine is running at Bulk_Loop_Write. It cause Status Machine couldn't run to next state. Why FlagA & FlagB doesn't work while FlagC & FlagD work well?

Thank for your help!

Tomsen