USB superspeed peripherals Forum Discussions
Hi!
I am using CX3 for USB 3.0 webcam development.
In the project, still image capture need to be triggered both
- by PC (Window 7 or 😎 application SW.
- by camera device's snapshot button.
SW triggering is done, but HW triggering cannot find how.
As I assume, the sequence will be
[raise endpoint interrupt to HOST] -> [Host issue still capture event] -> [remaining same as SW triggered case]
But I cannot figure out how to code for it.
Can someone show me some example code?
Thanks.
Show LessDear Sir,
I want to use CX3 to transmit UVC video,CX3 also has other functions,for example,
1. scan keys or buttons input, how to send key events or other customized events to PC?
2. PC can send some customized commands to CX3? how to do that?
Best regards!
David
I have discovered in the forum history two examples of UVC with USBUART combined.
I am trying to find the latest version of this example, as it isn't supplied as part of the SDK.
Could you please supply me with the latest copy of this example as I want to use the ov5640 camera via USB and serial data via USB
Regards,
Dave
Show LessIn our system FX3-CYUSB3014 + SDK 1.3.3 we use the following transfers at the same time:
BULK-OUT: to write data from the PC to the device-TFT-display with DMA
BULK-IN: to read data from a camera to the PC with DMA
CONTROL-GET: to read cyclical a touchpad on our device
If the connection is USB2.0 we found the following issue:
(analysis with an USB bus analyzer)
- The system is running well for a while
- suddenly a CONTROL-GET fails with "Turnaround Timeout Error" and "BAD CRC"
- The PC makes a second try to read the data and get the data with correct CRC but with the first 4 bytes wrong
- After the first occurrence of this error all of the following transfers CONTROL-GET and BULK-IN!!! have 4 wrong bytes at the start of each data record
The BULK-OUT to the TFT is further running well
To reset the error we have to restart the complete system
questions:
- any idea what happens or how to further investigate the problem?
- it seems the error is not in the firmware but in the hardware (USB20-SIE, USB20-TP) because it occurs in CONTROL-GET (firmware) and BULK-IN (hardware-DMA) at the same time in different pipes (EP0 and EP3). Is there a possibility to reset the SIE and/or the TP with out reset the entire system
- it is possible to detect by the firmware such a hardware error and how to react correctly. At the moment I send data and do not detect the problem in the firmware, only on the PC side
The error was observed until now only with USB2.0 (not USB3.0)
The error was observed only on some PC's (WIN10)
Thanks for any help
Show LessWhen I download the firmware of slavefifo to CYUSB3014,the USB Control Center show as the high speed.But I have set the connection as super speed.I don't know how to solve it.Can anyone help me?I would be grateful to you.
Show LessHow do I communicate between FX3 and Host PC in the UVC by using vendor command interface?
Hi.
I'd like to vendor command command communication between FX3 and Host PC in the UVC.
When I used the below host application code, the FX3 does not response.
USBDevice = new CCyUSBDevice(NULL); // Create an instance of CCyUSBDevice
How do I communicate between FX3 and Host PC in the UVC by using vendor command interface?
Hi all
I updated my PSoC Creator to latest Version 4.0
Open my old Project with an CYPD4225 on it.
Got a message: "Projects with outdated devices".
What should i do?
If I select yes I can choose between 4 CCG4 Controller. But only two with Dual Port.
CYPD4226 and CYPD4236
But I can`t find a Datasheet to this two controllers.
Should i downgrade my PSoC Creator?
Br Oliver
Show LessI am working with a FX3 firmware for communication board
which has a FX3 connected to a FPGA via GPIF II, and I have some trouble.
In this system, FX3 relays data from FPGA to USB with DMA.
Configurations are as following:
1) GPIF II is configured as Slave FIFO mode.
2) DMA type is CY_U3P_DMA_TYPE_AUTO
3) FPGA asserts "EOD" signal when FPGA stops producing data.
GPIF II is configured to "COMMIT" buffer when GPIF II receives "EOD" signal.
4) The number of DMA buffers is 8.
5) FPGA waits to transfer data while "DMA_Ready" signal is not asserted.
My probrem is as following:
1) DMA channel doesn't work after receiving "EOD" signal.
2) PC side only receives data until first "EOD" signal is asserted.
3) CyU3PDmaChannelGetBuffer returns code 0x47 (71) CY_U3P_ERROR_INVALID_SEQUENCE.
4) It seems that DMA transfers from FPGA to DMA buffer are done 8 times - that is number of buffers - using "EOD" signal 8 times.
Is there any setting I have to configure before using "COMMIT" function of GPIF II,
or any procedures FX3 firmware have to do after a buffer is committed?
Any hints are appreceiated.
------------------------------------------
*This is my code to configure DMA channel:
static void ReceiveDataStream_DMA_Initialize( uint16_t size ){
CyU3PDmaChannelConfig_t dmaCfg;
CyU3PReturnStatus_t apiRetStatus = CY_U3P_SUCCESS;
const int WATERMARK_OFFSET = 4;
//Create GPIF II to USB channel
dmaCfg.size = size * 8; //size is 1024 with USB 3.0
dmaCfg.count = 8;
dmaCfg.prodSckId = GPIF2_RX_STREAM_PRODUCER_SOCKET;
dmaCfg.consSckId = EP_RX_STREAM_CONSUMER_SOCKET;
dmaCfg.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaCfg.notification = 0;
dmaCfg.cb = NULL;
dmaCfg.prodHeader = 0;
dmaCfg.prodFooter = 0;
dmaCfg.consHeader = 0;
dmaCfg.prodAvailCount = 0;
apiRetStatus = CyU3PDmaChannelCreate (&glReceiveDataStream_DMA_Handle,
CY_U3P_DMA_TYPE_AUTO, &dmaCfg);
if (apiRetStatus != CY_U3P_SUCCESS)
{
ErrorHandler(apiRetStatus);
}
apiRetStatus = CyU3PGpifSocketConfigure(
GPIF2_RX_STREAM_THREAD,
GPIF2_RX_STREAM_PRODUCER_SOCKET,
dmaCfg.size - WATERMARK_OFFSET,
CyTrue,
2
);
if (apiRetStatus != CY_U3P_SUCCESS)
{
ErrorHandler(apiRetStatus);
}
apiRetStatus = CyU3PDmaChannelSetXfer (&glReceiveDataStream_DMA_Handle, 0);
if (apiRetStatus != CY_U3P_SUCCESS)
{
ErrorHandler(apiRetStatus);
}
return;
}
I am a student working with the EZ-USB FX3 (CYUSB3KIT-003), and I have never really worked with devices like this before, so I just had a beginner's question about setting it up: how do I go about configuring the PMODE pins for USB Boot? I've seen references to them in several forum posts, and read all I could find in the datasheets about which pins are 1 and 0, etc, but I don't know how you actually access and change them. I noticed two pins on the FX3 board that had PMODE labeled on them, but I tried connecting them with the red headers included in the box and it didn't seem to make a difference when I plugged in the board.
I am basically just trying to figure out how to use this board with little prior experience, and this seems to be a roadblock in getting there.
Any and all help is appreciated!
Show LessI have this state machine segment, I use LV to trigger the DMA to DR_DATA onto the parallel data bus. I capture the data using the timing
relationship similar to "cs_n = 0 & we_n = 0"--> "data" of SRAM.
In the logic analyzer I could see an extra 32-bit of unknown data. What's the latency for me to capture the data?
When I set the data count to 16384 with incr = 4, after pulse the LV for 4096 pulses, the state machine stays at DL_WAIT instead of moving onto DOWNLOAD_DONE via DATA_CNT_HIT. Anything wrong with my state machine?
Show Less