USB superspeed peripherals Forum Discussions
Hello,
If the amount of data that should be transmitted to the PC is more than a single FX3 can handle, can we use 2 FX3s at the same time? In theory this should be okey. do you think that problems can arise on the PC side of software?
Show LessHi,
I am making an USB Composite device (UVC + CDC). The device got registered properly and among the two, camera is working successfully. However, when I opened the serial port (CDC) it does not read anything.
In the firmware, there is a thread which acquires USB buffer and commits it. The function CyU3PDmaChannelGetBuffer returns with CY_U3P_ERROR_TIMEOUT always.
I have tried different sizes and buffer count for DMA during the channel create.
I have gone through some other posts regarding the DMA time out. However, I did not get any solid solutions from them.
I am using CX3 Denebola with OV5640 sensor.
Attaching the sources.
Show LessHi,
I am trying to use JTAG debugging with a custom KMDF driver but it does not work.
Using the same FX3 firmware (just changing Vendor ID/Product ID to be Cypress and using Cypress driver) I can run the JTAG debugger successfully.
Is there a special request to execute to enable the JTAG?
Any idea what can be wrong?
Thanks, Malikcis
Show LessHi, I want to get the statue (high or low) of a GPIF port, what is the API function? Dose CyU3PGpioGetValue() function work? What is the difference between GPIF and GPIO?
Show LessHi,
I am working on the Slave FIFO stream-in of the FX3 superspeed explorer kit. I am asking if the firmware can work with 8-bits since I noticed head file only had 16 /32 bits choices. The GPIF II has the 8-bits choice.
1. How shall I modify the head files?
2. If system was configured with 32 bit, but each sending data size (from FPGA to FX3) only has 8-bit (D0-D7), is this the reason cause the 997 error?
Thanks
WB
Show LessHi,
I am trying to test how the DMA_Ready flag works. For that I use a very simple interface and state machine, that would allow me to monitor the flag. See the attached GPIF designer screenshots for the interface and the state machine.
I have setup with a DMA channel from the GPIF to USB, in auto mode. The channel uses 2 buffers, each with size 16 bytes.
The GPIF clock is provided externally, using the positive clock edge.
On the attached waveform snapshot, cursor A indicates the point when WR goes low. After that there are 4 clock cycles that read 4 32 bit words (16 bytes), and on the third positive clock edge the DMA_Ready flag goes low.
Cursor C is when the DMA_Ready goes high again, after the socket has switched to the second buffer. 4 more words are clocked in, and then on the first positive clock edge the DMA_Ready goes low. There is not 3 clock cycles delay this time - only one. Why? Is this normal?
Thank you,
Dimitar
Show LessI am laying out a new pcb for FX3 and was wondering if I could get away with 6 layers only, instead of 8 layers as used in the development kit? The reason for this is strictly cost reduction WITHOUT compromising data transfer speed and signal quality.
We are using the full 32-bit GPIF bus for communication between FX3 and a slave device, and there are hardly any unused pins (5 or less) on the 121-ball 0.8 mm FX3 IC.
Thanks
Mak
Show Lesshi i'm change an75779 example into 32bit data width
the device is emulated and data is transfered about few package then stoped (capture by bus hound) the fx3 program is runing "tx_thread_schedule" & "tx_thread_system_suspend" threads
but 8bit/16bit firmware works fine
then i change my program into uvc + slavefifo from "FX3 firmware for streaming UVC Data from an FPGA" this post
i found the flaga and flagb didnt change when i try to write data into fifo. i checked all ping is fine (rd/oe/pktend are high addr/wr/cs are low)
what the problem should be?
Show LessI have a design that sends 8-bit data from an FPGA to the FX3. I have a manual DMA channel setup that has 4 buffers. When the application starts I can see from UART debug that it fills the 4 buffers but then it stops. The FLAGA goes low and no more data can be sent. Any idea why this is happening? Is it because the host isn't requesting this data so it just waits until it does? I am using the slave fifo code but I am using my own FPGA logic.
Thanks
Jon
Show Less