USB superspeed peripherals Forum Discussions
How could USB3.0 set the maximum number of retry transmissions when data transmission is wrong?
I am designing a rigid-flex board with the FX3 Super Speed controller.
Is it possible to route the 9 USB 3.0 lines on Kapton before reaching the USB standard connector? Is there any extra rule that I need to follow in this particular case other than matching the 90 Ohm specification for the impedance?
Show LessHello,
Im using FX3 CYUSB3Kit-003 on Windows 10, which is the SuperSpeed Explorer Kit. When adding J4 jumper to the board in the device manager it shows up as "Cypress FX3 USB BootLoader Device". Which is fine. After i program the board with my development firmware it uses the Cypress VID and PID from the StreamerExample and thats how it shows up in the device manager "Cypress FX3 USB StreamerExample Device". I am using the driver installed in the following path C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\driver\bin.
What i want is when i program it with my development firmware i would like the friendly name to be changed to a custom name for the product. When i tried to edit the .inf files in the above driver\bin folder and placed my own string, Windows 10 would fail to install that driver because that new string was not part of the Driver Signature. So my question is this is there a way i can change the friendly name without having to get a certificate and having to submit the generic Cypress driver to Microsoft again for resigning?
Show LessIs there a source with more information on the error count fields for the structure CyU3PMipicsiErrorCounts_t as used by the CyU3PMipicsiGetErrors function. Some are fairly intuitive to me but specifically I'm wondering what the frmErrCnt means. I'm getting Framing Errors about the rate that the image sensor is configured to send frames. I'm not sure exactly what the cause is or how to correct it though. All the other error counter fields are 0. I played around with phy time delay and can cause errors with sync bytes and start patterns but as far as framing errors I haven't been able to get them to go away.
Any thoughts?
Thanks.
Show LessI am using the EZ-USB FX3 development board. I want to download firmware image to I2C EEPROM, but ,it always show Promgramming of I2C EEPROM Failed.
the EEPROM is 24LC1025.(I tested it with UsbI2CDmaMode,the chip works well )
SW25=off,off,on,on.
SW40=on,on,off,off.
J42 and J45 pins 1-2 are shorted on the DVK board.
And,the size of img is less than 128KB. ie USBBulkLoopAuto.img=121KB
Hi:
I want to configure a FPGA of altera , AN84868 is referenced. but i want use the quartus II software to download FPGA code and debug.
so i think i need the altera usb blaster driver ,but how can i make match AN84868 and the altera usb blaster driver ,where that i need modify. do you see what i mean ? do you have other better ways .can you help me , thanks.
Show LessHi,
Has anyone ever created an SDK project that I can use to print data read with FX3 into a txt file? - I would like to use the STREAM_IN feature of the device.
Thanks in advance
Best regards
Alessandro
Show LessHi all,
I have observed that the FX3 driver installed with SDK is not completely having the driver for "Cypress USB BootLoader" the default bootloader running with FX3 with VendorID="04B4" and ProductID="00BC" . I have opened the driver "cyusb.inf" file present inside the driver folder of FX3 SDK installation location, I did see that the PID of Bootloader is mapped to "00F3". If this value is "BC" instead of "F3", device is detected properly. So, Please let me know if there is cypress signed driver with BootLoader assigned to "00BC" or any other suggesstions for solving this issue is also welcome.
Thanks,
KCNGP
Show LessHello.
I try to organize Slave FIFO Interface with CYUSB3KIT-003, CYUSB3ACC-006 HSMC Interconnect Board and Altera Cyclone III Starter Board as described in AN65974.
I've compared pinout of CYUSB3ACC-006 with Altera's Starter Board pinout -- and it doesn't match. Some signals from CYUSB3KIT-003, which is needed for Slave FIFO Interface, don't reach FPGA. For example, signal FLAGA. In GPIF II Interface it is CTL[4] (picture 1). CTL[4] on CYUSB3ACC-006 HSMC Interconnect Board attach to pin №100 (picture 2). But on Altera's Starter Board pin №100 connects to 12V and doesn't reach FPGA (picture 3).
So, I don't understand, how Slave FIFO Interface can work? Maybe I miss something.
Look forward to hearing from you. Thanks.
Pic 1 from "CYUSB3014 EZ USB FX3 datasheet", page 32.
Pic 2 from "630-60197-01_CYUSB3ACC-006_HSMC_INTERCONNECT_BOARD_SCHEMATIC", page 3.
Pic 3 from "cycloneiii_sb_3c25", page 11.