USB superspeed peripherals Forum Discussions

Hi,

We want stream video data from image sensor with UVC on isochronous mode in Super Speed(USB 3.0).

We are referring to the AN75779 example code, but this exmaple is using Bulk mode.

Our camera environment  is 1280x720 / 30 fps / YUV format(uncompressed).

So we need about 55MB/s(1280x720x2x30x8) bandwidth.

As I know,

due to UVC driver constraints, FX3's maximum bandwidth on ISOC endpoint under UVC for USB 3.0 in Windows 7/8 is 24MB/s.

Only with Windows 10, maximum bandwidth will be 24MB/s X 16 = 384MB/s.

(See AN75779 document 4 page Note..)

Q1 >
In the above environment, Should the host use only Windows 10 for sufficient bandwidth support?
If the host use windows 7/8, is our camera unusuable on isochronous mode?
Although it is available, is it operating up to 24MB/s?

Q2 >
For isochronous mode setting, Can I change only the endpoint configuration on descriptor file in example code? 
Do I need addtional work? (eg. data packet, thread callback configuration..)

Thank you in advance.

I am trying to create a video interface to FX3 GPIF, based on AN75779.  I use FPGA to create simple video signals FV and LV. LV is short with just 8 data (and 8 clks) per LV and 4 LV per FV.  GPIF PCLK  is driven by FPGA.  GPIF counters limit are set to 7 so that it coincides with the 8 data per LV.

To study the state transitions, GPIF outputs '1' to GPIO when in following states highlighted in yellow.  I can only monitor 5 states as GPIF Designer allows maximum only 5 GPIO as output.

Here is the waveform captured by logic analyzer:

I notice there is a extra clk with no valid state when transiting from PUSH_DATA_SCK0 to LINE_END_SCK0.  From GPIF designer, there should NOT be a state between  PUSH_DATA_SCK0 and LINE_END_SCK0.

Then I redo the test.  i set GPIF cnt limit to 7, so that incoming data will overflow socket 0 and force GPIF to capture using socket 1.  State transition from PUSH_DATA_SCK0 to PUSH_DATA_SCK1 is correct except there is again 1 unknown state between them.

Question, will the incoming stream of 8 data (in 8 clks) be correctly captured OR will the extra unknown state  cause the last data to be missed?

Question, why does this unknown state happen?  It does not occur all the time as I can see other state transition without it.

Regards,

Neo

Hello,

in the "HowToInterfaceMIPI.pdf" document you say that the maximum supported PCLK is 100 MHz.

We have a raw12 data format with 4 data lanes and maximum data rate of 400Mbit/s at each lane transferred using the CSI2 interface.

Is it possible to configure the MIPI CSI2 controller so that we can transmit our data in parallel over the GPIFII interface using a bus width of 24bit?

Thanks in advance!

I am working on a CX3-based product, and I need to provide a unique serial number for each device.  I would prefer not to have an additional step during manufacturing which write a unique value into non-volatile memory.  Does the CX3 have any sort of unique identifier that I can access through a register that I could use for this purpose?

Thanks.

Hello

Please recommend if there are any reference design of a USB bridge design that can connect 2 USB 3.0 host controller?

Communication: USB3.0 (SS)

Eg.

https://www.sanwa.co.jp/product/syohin.asp?code=KB-USB-LINK4

Best Regards

Hi,

I would like to step through the example firmware for EZUSB explorer kit.

If I just connect PC to the USB2.0 port on EZUSB and run CYPRESS EZ USB suite, is it enough to do this?  If not, what other hardware/software tools do I need?

Neo