USB superspeed peripherals Forum Discussions
I have EZ-USB FX3 superspeed explorer kit. I browse and test several examples with the SDK. I have a small OLED device with I2C interface and I want to connect the device externally with the kit using SCL-SDA pins. How can I connect and program peripheral controller to use the OLED to display some text/image?
The OLED device I have used earlier with Arduino and now I want to use the display device along with other devices to FX3 controller.
I notice that 4-wire designs are absent from AN70707 PCB Guidelines. Can you please verify the feasibility of my proposed 4-wire microSD connections? In particular, that I am free to ignore signal WP, which does not exist on my microSD connector. VIO2 working voltage is 3.3V. What considerations are required to lower this voltage to 1.8V?
TIA!
Show LessHi,
It would be really nice if we can have an event driven receive event handler in CyUsb library..
Like Device Attached and Removed, if we have like that, there may be no need to use thread.
Just my suggestion.
Regards,
Mike
Show LessHello,
I'm using CYUSB3014 working with FPGA. One Bulk ep is used as the data interface, and EP0 is only used to transfer control commands that is of 4 bytes length of both read and write direction.
When testing the system, I found that if EP0 is reading data from FX3 to PC during data transfer, FX3 could fail after several thousands of runs. When it fails, EP0 and streaming doesn't work any more, and the device cannot be listed if I restart the application(also cannot be seen on the control center, but still can be seen in the OS device manager). Even I reconnect the U3 cable, it still cannot be recognized by the driver. Only if I restart FX3, it can work again. It seems that the driver or the firmware is crashed.
I'm using CyAPI on C++ console application. One thread is streaming thread, and the other thread continuously to send read request to EP0 with no interval:
m_USBDevice->ControlEndPt->XferData(ControlBuffer, XferLen, NULL);
There is no other thread calling XferData of EP0, And there is no EP0 operation called inside the streaming thread.
If I write instead of read from EP0, it does not fail. If I read in the callback function called from the streaming thread after a frame is transferred, it also does not fail. But in real application, EP0 transfer could be called during streaming. If I keep streaming thread running but no data is transferred from FPGA while read action runs continuously, it also doesn't fail.
Thanks
W.D.
Show LessI would like to do Soft Reset (CPU Reset) as mentioned in the data sheet of FX3 . How to implement it?
Hi All
So I'm currently using the SlaveFIFO firmware for the FX3 to send and receive 32 bit data packets from a Master FPGA. Each transaction involves a packet sent from the PC software then once read by the FPGA determines how many 32 Bit words should be returned. As the number of words returned is variable, I have been using Pktend to reduce the latency in the over all transaction, and this is where my problem lies (my buffer size is 16k and only 1 DMA buffer).
If in the first transaction the PC software requests a set amount of words, lets say 40, the FIFO transaction will work fine. However if in the next transaction the PC software requests any more words than previously requested, like 41, then the transaction will fail, and Xferdata will return false to the Bulk In Endpoint. So far I've tracked it down to the FX3 firmware, whether its in the GPIF or actual firmware I'm unsure.
Please let me know if I can provide any other helpful information
Kind Regards
Ricky
Show LessHi,
I have a system that controls externally frame time and frame rate of my camera.
At UVC class frame time is defined by using descriptors of frame and uvc.
Can I use a specific frame rate (30 fps) with a camera with lower or higher frame rate( i.e 20 fps or 50fps). If not, is there a chance to control frame rate externally (with another controller) in UVC example ?
Show LessJust like FTDI FT600Q-FT601Q(USB 3.0 to FIFO Bridge).
Is that possible to configure FX3 to receive video stream from Host, and then output parallel data via GPIF II.
Design GPIF to support : ((Parallel FIFO bus clock / Control signal / data bus output)
EX:
- output Pixel clk
- output FV( Vsync )
- output LV( Hsync )
- output Data bus (8 ~16bits)
Show LessMy sensor has 1600 pixels/line. Each pixel is 8 bit. My understanding is that if I set MIPI receiver to deserialize data into RGB888 format, then the bus will be 24-bit wide (three pixels per clock will be transferred). Under these assumptions, what is correct value for DATA_COUNT? 1600 is not divisible by 3.
Please advise,
Show Less