USB superspeed peripherals Forum Discussions

Hello, What is the use of source code that created in the CX3 configuration utility. What if I want to change USB descriptors or something, is it OK to edit code that created in project folder.

I have been working with CX3 to implement a USB camera, and I have the Denebola kit to try my modifications. These are my previous posts: #1 and #2.

The problem right now is to achieve the correct MIPI configuration for everything to work. The problem is, I don't have enough information to change the settings.

I am trying to work with a Sony IMX219PQ, with these parameters:

• MIPI CSI clock = 1368 MHz
• THS prepare = 47
• THS zero = 87
• Hblanking = 1528
• Vblanking = 683
• REFCLK = 19.2 MHz

Since these values lead to impossible ranges, I have modified them: THS zero = 100, Hblanking = 200, Vblanking = 200.

But the CX3 Receiver Configuration application always shows an error:

Since the values are in the right ranges, I don't know why am I getting this error.

What is the use of the values on the left side (MIPI CSI2 Inputs From Image Sensor) if the ones that are being used are obtained from the right section (CX3 MIPI Interface Configuration)?

Why does that error shows up?

Why does a larger Hblanking value leads to a larger Output Pixel Clock min value?

Hi All,

I'm running my FX3 chip in conjunction with a cyclone FPGA, using the SlaveFIFO firmware. When i try and use the BulkOutEndPt.Xferdata to write data to my FPGA it seems to work fine most of the time. However if the number of words written is specified as 128,256,512,1024... ect then the DMA flag to begin my FPGA FIFO state machine, doesn't trigger. Its also worth noting that, if i then proceed to do a read, the 512 (or other specified length) write will happen then the DMA flag is triggered.

Cheers

If I configure the MIPI block as RAW10 (as shown in the code below), but the GPIF bus is set to 8 bits, what will happen?

My guess is only the first 8 bits of each pixel get sent.

i.e. Camera sends this info for each pixel: Pix[9:0]; MIPI block sends to GPIF only Pix[7:0]

Is this correct?

MIPI configuration:

CyU3PMipicsiCfg_t cfgUvc1080p30NoMclk =  {

CY_U3P_CSI_DF_RAW10,      /* dataFormat   */

2,                          /* numDataLanes */

1,                        /* pllPrd       */

62,                          /* pllFbd       */

CY_U3P_CSI_PLL_FRS_500_1000M, /* pllFrs      */

CY_U3P_CSI_PLL_CLK_DIV_8,    /* csiRxClkDiv  */

CY_U3P_CSI_PLL_CLK_DIV_8,    /* parClkDiv    */

0x00,                        /* mclkCtl      */

CY_U3P_CSI_PLL_CLK_DIV_8,    /* mClkRefDiv   */

1920,                        /* hResolution  */

0x01                        /* fifoDelay    */

};

GPIF configuration:

status = CyU3PMipicsiGpifLoad(CY_U3P_MIPICSI_BUS_8, ES_UVC_DATA_BUF_SIZE);

Hello.

Please, tell us how the communication and initialization of the device are going on USB3.

For example: initial Hight speed features after detect connection Full speed device.

How does it device recognize that it is connected to port USB3 or to port USB2?

And how does the computer determine that the device USB3 is connected to its ports or USB2 device?

Where it can be read?

How does this happen in FX3 / CX3?

GPIF II - FPGA interface

GPIF is sychronous master 8bit multiplexed address data

Address is 24 bit, data is 32 bit

Clock can go in either direction

Output 3 controls signals to FPGA

ALE - address latch enable, asserted low

DEN - data enable for reads and writes, asserted low

LWR - local write, high for writes, low for reads

ALE, A[23:16]

ALE, A[15: 8]

ALE, A[ 7: 0]

WAIT - if read operation LWR = 0

DEN, D[31:24]

DEN, D[23:16]

DEN, D[15: 8]

DEN, D[ 7: 0]

    ..

Repeat data transactions if burst, address auto increments

Hello,

I am using cyusb3035 fx3s,i have interfaced fx3s with two spi flash(same specification and separate chip select) through spi interface.

one flash is for booting the fx3 and other is for data storage.can i interface fx3s with two spi flash?will it cause problem for booting if i do?let me know.

thank you,

Hello.

Could you please let us know OS supported by CYUSB3033-BZXC?

Best Regards.

Yutaka Matsubara