We use CYUSB3KIT-001 to connect to TypeC HUB and encounter FX3 streaming media transmission failure problem.
A few transfers were successfully transferred at first, and then the transfer continued to fail.
Once the transmission fails, the transmission cannot be continued.
The same problem occurs bulk in and bulk out.
But using USB storage for transfer is successful.
We want to ask:
1. The reason for the transmission failure?
2. Is there any way to solve this problem?
3. What is the difference between Streamer and Storage transmission?
AMCAP application unable to display any data on its screen. On PC side we are able to see data through USB analyser but not on the AMCAP application.
Image sensor: AR1335
AR1335 configured with : RAW8 , 640*480 @ 2FPS and CSI clock-160MHz
CX3 MIPI Configurations :
INPUT video format : RAW8
OUTPUT video format : 24bit
640*480 @ 6FPS and CSI clock-160
CyU3PMipicsiDataFormat_t dataFormat : CY_U3P_CSI_DF_YUV422_8_2 (also tried CY_U3P_CSI_DF_RGB888 , CY_U3P_CSI_DF_RGB565_2 )
Number of bits per pixel: 16 (8 bit also tried )
Width in pixel: 320 (640 also tried)
0x59, 0x55, 0x59, 0x32, /*MEDIASUBTYPE_YUY2 GUID: 32595559-0000-0010-8000-00AA00389B71 */
0x00,0x00,0xe1,0x00, Min bit rate (bits/s):14745600=640*480*8*6
0x00,0x00,0xe1,0x00, Max bit rate (bits/s):14745600=640*480*8*6
0x00,0xb0,0x04,0x00, Maximum video or still frame size in bytes(Deprecated) 640*380
CX3- log :
TimeDiff = 10686 ms FPS = 2
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 31 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 32 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 33 Frm_Sz = 691200 B
Prod = 18 Cons = 18 Prtl_Sz = 28512 Frm_Cnt = 34 Frm_Sz = 691200 B
I have the following system: FPGA -> FX3(superSpeed explorer kit)->PC
I send counter from FPGA, but on pc i get shuffled data in multiples of packet size (1024)(1.png in attachments)
I try different parameters of DMA counts, DMA buffer size, but always the same
FX3 work on modified FIFO sync mode(from examples)
I'm not quite sure what other information to provide, so ask, I'll attachShow Less
I can't speak English well.
In the FX3 SlaveFIFOSync 5Bit example, we want to use 6 ENDPOINTs.
endpoints 0x1, 0x2, 0x3 works well.
But endpoints 0x81, 0x82, 0x83
BULK IN transfer
BULK IN transfer failed with Error Code:997 occurs.
I checked the 5bit FIFO ADDR
From 0 to 31, the flag of the INPUT endpoint did not occur.
Only output endpoint 0x1~0x3 operates.
If you change the positions of CY_U3P_PIB_SOCKET_0 and CY_U3P_PIB_SOCKET_4, this time they all change to INPUT and OUTPUT does not work.
Can you explain what the problem is?
I want to use all 6 ENDPOINTs
Thank you.Show Less
I am writing firmware for the CX3 to interface a new sensor and am running into a confounding problem. My program behaves differently when I rearrange the order of functions in my C source code. This leads me to believe I have some memory corruption issues. I found the CyU3PMemCorruptionCheck() and CyU3PBufCorruptionCheck() functions in cyu3os.h and am trying to use them in my program. But when I do, the linker complains they are not defined. In what library are they defined?
I'm trying to use the AN75779 project as a baseline to set up my MT9P031 as a UVC camera.
Here's what I did:
Modify GPIF state machine: changed to 16 bit wide bus with one clock per pixel, changed LD_ADDR_COUNT and LD_DATA_COUNT limits to 8183 to account for this. Changed the active clock edge to falling.
In order to fake the YUY2 I tied data 15 high and 14:8 low so the upper byte would be 0x80. Then I just attached my most significant 8 bits of my camera bus to data lines 7:0.
Overhaul to the I2C in sensor.c code. The MT9M114 uses two bytes of register addresses in its protocol while the MT9P031 only has one so I had to get rid of the upper address byte in all the functions. I got rid of all of the configuration for MT9M114 and only wrote in commands to set my sensor up to run 720p at whatever rate it runs. I figured initially setting the sensor up to do 720p to match the existing project would be the path of least resistance.
I have a 24MHz clock and the datasheet suggests it would get 60fps with 96MHz so I assume it's actually going to give 15fps instead of 30.
In the UVC Descriptor C file, I've tried just leaving everything alone, as well as increasing the frame time to double or four times the original (so 0xA2C2A or 0x145854) to account for a lower FPS but nothing is helping.
The result is that Windows recognizes the device as a camera and I'm able to select it with the Windows camera app, and I see some response on the debug serial port when I do select or de-select it.
With the additional debug print enabled, I see "UVC: Completed (n) frames and 0 buffers."
Ultimately though I just get a black screen.
Do I need to use the PLL to increase my clock rate to actually achieve 30fps? Or do I need to adjust the minimum bitrate in the descriptor to reflect what the camera actually puts through?
Or am I missing something else?
Thanks in advance!Show Less
Now I am trying the develop a product with CYUSB3014, and I am reading 2 documents to help me understand it.
<<001-76074_EZ-USB_FX3_Technical_Reference_Manual.pdf>> and <<001-92220_AN75779_How_to_Implement_an_Image_Sensor_Interface_with_EZ-USB_FX3_in_a_USB_Video_Class_UVC_Framework.pdf>>
And I find a problem.
In the chapter 7.11 of Techincal reference manual, there is a flag named DMA_RDY_TH0. And DAM_RDY_TH1.
According to my understand, this flag is used to solve the GPIF's problem between data transfer and the DMA buffer switch in different thead. When the thread is swith to used a free DMA buffer, this flag is used to pause the data transfer.
So if the GPIF used 2 thread to receive the data, this flag should be used.
But in the AN75779, I did not find any information about this flag. So does it mean that there is a loss of data during the 2 thread switch in AN75779 example?
I'm looking for an example that streams parallel data back to a PC using the GPIF on an FX3. Does such an example exist? I'm attempting to build an SRAM sniffer.
I experience an FX3 EP_IN data transfer stop problem. Our design is based on the uvc_cdc example design.
UVC channel is auto_many_to_one DMA, the setting is:
dmaMultiConfig.size = 16384;
dmaMultiConfig.count = 4;
dmaMultiConfig.validSckCount = 2;
dmaMultiConfig.prodSckId  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_0;
dmaMultiConfig.prodSckId  = (CyU3PDmaSocketId_t)CY_U3P_PIB_SOCKET_1;
dmaMultiConfig.dmaMode = CY_U3P_DMA_MODE_BYTE;
dmaMultiConfig.notification = CY_U3P_DMA_CB_PROD_EVENT | CY_U3P_DMA_CB_CONS_EVENT;
dmaMultiConfig.consSckId  = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_SOCKET_UVC);
dmaMultiConfig.prodAvailCount = 0;
dmaMultiConfig.prodHeader = 0; /* 0 byte UVC header to be added. */
dmaMultiConfig.prodFooter = 0; /* 0 byte footer to compensate for the 12 byte header. */
dmaMultiConfig.consHeader = 0;
dmaMultiConfig.cb = CyFxUvcDmaCallback; /* use Capture mode's DMA callback */
apiRetStatus = CyU3PDmaMultiChannelCreate (&glChHandleUVCStream,
CDC channel is manual DMA, the setting is:
/* Create a DMA_MANUAL channel between UART producer socket and USB consumer socket
* Use a smaller buffer size (32 bytes) to ensure that packets get filled in a short time.
dmaCfg.size = 32;
dmaCfg.count = 32;
dmaCfg.prodSckId = (CyU3PDmaSocketId_t)(CY_U3P_LPP_SOCKET_UART_PROD);
dmaCfg.consSckId = (CyU3PDmaSocketId_t)(CY_U3P_UIB_SOCKET_CONS_0 | CY_FX_SOCKET_CDC);
dmaCfg.notification = CY_U3P_DMA_CB_PROD_EVENT;
dmaCfg.cb = CyFxUART2USBDmaCallback;
apiRetStatus = CyU3PDmaChannelCreate (&glChHandleUarttoUsb,CY_U3P_DMA_TYPE_MANUAL, &dmaCfg);
Test setting is:
An app from host PC connect with FPGA through CDC channel. This app enable FPGA to generate UVC traffic, after this the app doing nothing, so there is no traffic flow on CDC channel.
Window "Camera" play video FPGA generated (sent to host PC through UVC channel). The rate is about 320M Bytes per second (90% of GPIF bus bandwidth)
The traffic stop is random, some time in a few minute, sometime a few hours, most time never happens. I am able to reproduce this problem by adding 4 hubs between host PC and device.
Most time when UVC traffic stop, CDC upstream traffic stop as well, CDC downstream traffic is still ok.
If I build FX3 firmware with SDK1.3.3, I can resume CDC upstream traffic by close and re-open host PC app(close and open uart port). UVC traffic can be recovered by changing video channel (in side FX3, uvc related endpiont and DMA channel will be deleted and re-created).
If I build FX3 firmware with SDK1.3.4, this problem will happen much much less often, but once happens, host PC apps freeze, I have to unplug USB cable to close apps, but in one time after about 20 seconds, CDC and UVC channel recovered by itself.
I used a USB analyser to capture traffic to and from FX3, there is no CRC error, the traffic stop is because FX3 send a NRDY transaction packet to host PC (there is no ERDY transaction packet send out by FX3 after NRDY)
Following is a screen shot of some captured data, there are about 30 to 50 unexpected transaction (in class view of usb analyzer) before NRDY, but they look the same as those good one.
Any one has any idea about this please give me a help, Thanks!Show Less