USB superspeed peripherals Forum Discussions

What is the average power consumed by a CYUSB3064 or CYUSB3065 device when streaming 1080p30 video over USB?

What is the minimum solution size (PCB area) for that application?

Thanks,
Michael

Hello people,

I was wondering if I can commit a buffer immediately after another has been committed (I know I can't commit the SAME buffer).The scenario is the following one: when I received the first frame buffer, I want to send another indepently from the frame buffer received. Then I want to sent the received one.

This is similar to the UVCAddHeader() function used to add the UVC Header and EOF at the beginning of a buffer. Although there are two main differences: one, as already mention, must be indepently committed. The second one, is that is committed twice: at the beginning of a frame and at the end of that frame.

Any input is appreciated.

Marc

Hello Everyone,

I want to create a project in which i need sound as well as video from the gpif, i am using EZ-USB FX3 board

Can you please provide an example for combine UVC and UAC and input taken from GPIF?

Thanks

Hi,

So I'm trying to understand the use of the 2nd Stage Bootloader and I'm having the following issue.

I program the 2nd Stage Bootloader into the I2C EEPROM for the FX3 and set up the jumpers so that it will attempt EEPROM first. This part of the project works, as on startup, the device enumerates as my custom bootloader with custom serial number and ect... However when programming the 2nd stage bootloader with my final firmware (a modified FIFO) the success rate is typically only about 80%. The only modification I have made to the Fx3BootAppGcc, is switching CyFx3BootUsbStart (CyTrue, myUsbEventCallback); to CyFx3BootUsbStart (CyFalse, myUsbEventCallback);, so to enable booting from the USB once the 2nd stage bootloader has enumerated.

Any advice on the poor success rate of programming my 2nd Stage Bootloader would be much appreciated!

Kind Regards

My questions on AN84868 configuring FPGA by FX3

1) In AN84868, if the FPGA has been configured by FX3, it will switch to slave FIFO mode. Does this mean the original codes can only configure FPGA for once? Is it possible to split channels, one channel is only for configuring. If this channel get the data from host, it means the configuration is expected,and the FX3 GPIO switch to configuration.

2) If the host have not send data to FX3 in AN84868, will the GPIO pins be tristate?

3) Will the GPIO pins be tristate when the reset pin is hold active.

The above questions come from my new plan: configuring kintex-7 FPGA by Master BPI mode on powering up and then FX3 can reconfigure FPGA as long as the host sends configuring data, the FX3 should also be in a slave FIFO mode to enable the transfer of data between FPGA and host when not in configuration. BPI and FX3 SPI will share some of FPGA pins. How to avoid conflict?

Thank you.

Hi ,

I'm using CY7C68013A and cyusb at the moment on window 7. However, I need to use the device driver on Window 10 with signed driver signature. I still can use my cyusb driver and window based software (which complied with old cyAPI.h and cyiocti.h) on Window 10 apart from needing to disable the driver signature option.

I really need to get sign the usb driver for Window 10.

My question is

1. Should I send my current cyusb driver to get signed Or

2. should I migrate cyusb to cyusb3 and get it signed.

   If I migrate to cyusb3, where can i get the header files and lib files?

   ( I'm not sure, is this the right download folder or not http://www.cypress.com/documentation/software-and-drivers/ez-usb-fx3-software-development-kit )

  Under the above link, I found one zip file called "CyUSB3_USB_Suite_Source.zip"

Thanks

Su

Hello, everyone.

I have related development experience with cyusb3014. In order to quickly integrate FX3 to our system, we used CYUSB3KIT-003. And it worked normally.

About three weeks ago, the CYUSB3KIT-003 was broken. and I bought another board to replace it. but something strange happened.

It couldn't work as expected. But we just used the same FPGA, same Verilog program, same connection with CYUSB3KIT, same fireware image file.

In our system, the synchronous slave fifo mode is used. However, FPGA cannot receive the data from FX3. according to the sampling of the signal line by chipscope,

the control signals are normal, that is, slcs is low, slwr is high, and sloe, slrd is low, flagc turns low. but there is no validate data on the data bus although  Control Center has sent data to FX3.

and for the previous broken board, the system just run normally.

why can this happen? how to figure this out? any ideas? Thank you very much.

yz

hi im using max2084evkit i powerup the board usb detect as westbridge in unkown port. couldnt update the driver softwre can you help me

Hello Everyone,

I am programming my FX3 using usb control center utility, and when i program using SPI flash mode it ask for img file and start programming of spi flash, but it stucks there only. how to solve this problem? i have connected jumper on PMODE J4. and it works fine when programming RAM and i2c eeprom but troubles me when programming spi flash. Please help

thanks