USB superspeed peripherals Forum Discussions

Hi,

I'm working on a project using CX3 and a custom sensor board. We also need the second interface to control the sensor registers. My application is generated by "CX3 Configuration Project".  I've integrated everything under "USB_DEBUG_INTERFACE" macro and created the thread for "UVCAppEP0Thread_Entry" from AN75779. The second interface is listed correctly in device manager, however, when I send data through "USB Control Center", the event is set in CyFxUvcAppDebugCallback, but the UVCAppEP0Thread_Entry doesn't see that event (I've put breakpoint inside the function) and when I press the "Transfer Data-IN" from USB Control Center, I get error code 997 (I assume its the timeout). Also, if I try again to send data to CX3, the CyFxUvcAppDebugCallback doesn't fire up anymore. Is there anything else I should integrate in my project from that example beside the macro and UVCAppEP0Thread_Entry? Maybe I'm missing something?

Thanks,

Ion Popa

I use FX3 SDK version 1.3.4 and want to create a new project from template. Following the instructions from the User Guide (section 2.3) I can create a new project from template. However I get errors in the new project, regardless which template I use. Errors like:

Any idea what's wrong here?

QUESTION: Is there a specific way that things must be configured on the computer and/or in the HLK in order for the Cypress driver to pass the HyperVisor Code Integrity Readiness Test?

We use the Cypress FX3 driver as part of our drivers.  In order for our firmware to load onto the Cypress device, we have to modify an INF file to tell what firmware gets loaded onto the Cypress chip. In turn, this requires us to be able to resign everything because the INF file was modified.

In getting the driver signed, we have to run the HLK (Hardware Lab Kit for Windows 10) tests, pass everything that is in the list of tests, and then submit the results and the EV-signed driver through a Hardware Development Portal to Microsoft (we used to cross-sign, but our new certificate no longer allows that).  In the HLK testing, the Cypress driver seems to be failing just one of the tests that is specific for Windows 10 64-bit environments (this test is not available if being tested in Windows 10 32-bit).  The test is called "HyperVisor Code Integrity Readiness Test"

In the test log, the following errors appear:

• WDTF_TEST : Non-zero Code Integrity statistic found: Execute Pool Type Count: == 2
• WDTF_TEST : Parsing Driver Verifier CI statistics log file detected Code Integrity FAILURES. (See the individual failures above.) Start Driver Verifier with '-flags 0x02000000' and a kernel debugger attached to the computer under test, and exercise the driver (use the driver) independently of running the test (separately from running the test) in order to identify specific failures.
• WDTF_TEST : For more information on HyperVisor Code Integrity Readiness Test failures, use the following link: http://go.microsoft.com/fwlink/?LinkId=787617

The specific SYS binary that is being used is the one that comes from the C:\Program Files (x86)\Cypress\Cypress USB-Serial Driver\DriverBinary\Vendor_Driver\bin\Win10\x64 folder of the Cypress USB-Serial Driver kit.

Is there a specific way that things must be configured on the computer and/or in the HLK in order for the driver to pass the HyperVisor Code Integrity Readiness Test?

Thanks for any help/advice provided

Hi,

My new design is a composite device which have 1 UVC channel and 2 UAC channels.

The UVC channel could support 3840x2160P30 @ NV12, and UAC are both work in 48KHz mode.

Now the problem is that after few minutes, one UAC channel will stop transmitting audio data and instead of transmitting some zero payload package to the host.

the other UAC channel will turn to transmit zero payload packet after half hour or one hour. The UVC channel always works fine.

So I checked the DMA channel status both of the UAC DMA channel status is in "CY_U3P_DMA_ACTIVE". Then I checked PIB, no errors found.

But on the GPIF interface the thread flag of the two UAC channel cannot asset anymore.

And I tried CyU3PUsbEnableEPPrefetch()  and CyU3PUsbEPSetBurstMoe(), nothing changed.

Because of that sometimes the device  halted and no response to the host, I think maybe there will be a stack overflow or something like that.

Any suggestion how I could locate the error?

Best regards

Wu 

Hi,

I am configuring CX3 for a 1851 * 900 resolution with 60 Fps in RAW8 format.

The details are shown in the image below.

The pixel clock needed as per configuration is 100MHz but when i select this in tool it shows up an error even though the entered value and max value are the same.

Could you please help me by confirming whether CX3 would work with a 100MHz pixel clock and the given configuration

Another problem was when i changed the output data format to 24 Bits.

Now the CSI clock is showing error stating it needs minimum 466Mhz and also the Pixel clock is showing errors.

Correct me if i'm wrong but pixel clock actually needed in this case would be 100/3 = 33.3Mhz. But the tool is not accepting this value.

Could you please verify these configurations.

Thanks in advance.

About connection line from V1P2 to VDD

Reference circuit diagram FX3_DVK_DEVICE_BOARD In the document

Although FB MPZ2012S601A is connected

Application note 001-86523_AN 70707_EZ-USB_R_FX3_TM_FX3S_TM_Hardware_Design_Guidelines_and_Schematic_Checklist_Japanese.pdf there is no description of the FB connection to the VDD line

Is FB necessary as the latest information to advance design? Is it unnecessary?