USB superspeed peripherals Forum Discussions
Hi,
I am configuring CX3 for a 1851 * 900 resolution with 60 Fps in RAW8 format.
The details are shown in the image below.
The pixel clock needed as per configuration is 100MHz but when i select this in tool it shows up an error even though the entered value and max value are the same.
Could you please help me by confirming whether CX3 would work with a 100MHz pixel clock and the given configuration
Another problem was when i changed the output data format to 24 Bits.
Now the CSI clock is showing error stating it needs minimum 466Mhz and also the Pixel clock is showing errors.
Correct me if i'm wrong but pixel clock actually needed in this case would be 100/3 = 33.3Mhz. But the tool is not accepting this value.
Could you please verify these configurations.
Thanks in advance.
Show LessAbout connection line from V1P2 to VDD
Reference circuit diagram FX3_DVK_DEVICE_BOARD In the document
Although FB MPZ2012S601A is connected
Application note 001-86523_AN 70707_EZ-USB_R_FX3_TM_FX3S_TM_Hardware_Design_Guidelines_and_Schematic_Checklist_Japanese.pdf there is no description of the FB connection to the VDD line
Is FB necessary as the latest information to advance design? Is it unnecessary?
Show LessHi,
I have an FX3 device and it is properly programmed by the included Cypress USB Control Center. I have downloaded and compiled the USB Control Center Source via the SDK download. Everything compiles ok, but when I try to use the FX3-->SPI_Flash option to program, I get an error from the following code.
StatLabel.Text = "Programming of SPI FLASH in Progress...";
Refresh();
enmResult = Fx3.DownloadFw(FOpenDialog.FileName, FX3_FWDWNLOAD_MEDIA_TYPE.SPIFLASH);
StatLabel.Text = "Programming of SPI FLASH " + Fx3.GetFwErrorString(enmResult);
Refresh();
The returned error is SPILASH_ERASE_FAILED
This error doesn't occur in the binary utility included with the SDK.
Using a USB analyzer, I can see that the same command C4H,1,0,0 is sent from both applications, but in my compiled version, it fails and in the utility (compiled by Cypress) the same command succeeds.
Any direction on this would be helpful.
Thanks
J.
Show LessHi:
I want to configure FPGA(altera) and want to make FPGA and PC communication by Cyusb3035.what will i do ? do you have examples of reference ?
Show Lesswe had a bank of buffers between the FX3 and the FPGA added since our Alpha design with the following notation.
BUFFERS U48, U51, U52, U53, U54, U56, U57
We not in the Alpha design � see schematic attached.
According to Greg’s notes
- Data flow is FPGA è FX3 for video and microphone (headset) transfers
- Data flow is FX3 è FPGA for headset audio output and in-system reconfiguration of the FPGA
BUFFERS U48, U51, U52, U53, U54, U56, U57 (SN74AVC8T245RHLR) are level shifters that should provide isolation between the FX3_+2.5V and +2.5V domains such that when only VBUS is present, +2.5V will not be present. When +5V(DC jack) is only present, FX3_+2.5V should be ~0V.
We believe there is a way to eliminate the buffers if we can configure the design correctly – see below.
To Cypress customer service
We are currently powering up the FX3 with an FPGA that is connected to the GPIF ports (DQ and CTL) however the FPGA is powered up separately to the same Voltage level. We would like to be able to bring up the FX3 with the FPGA powered down and not worry about back feeding power from the FX3 IO to the FPGA.. One suggestion is just use the FPGA power to supply VIO1, 2 & 3. If we implemented it this way, would PMODE and RESET_N still work? That would be a hardware fix that may or may not affect the reset function. Another possibility is more of a software fix and that would be to tristate the CTL and DQ ports as it powers up and leaving them tristated until we know the FPGA power is good. Please refer to page 5 of our schematic.
Thanks
Tom Minnis
Show Less
Hello Everyone,
I have created a state machine which is going to invalid state, but i haven't found why it is happening. Can you please tell me how to prevent from going to invalid state and if invalid state is achieved then how to return it to normal state?
Thanks
LD_DATA_COUNT is 8183
DE signal is data enable signal
Bus width is 16 bit
Buffer size is 16KB
Show Less
Hi:
I am using Cypress USB 3.0(CYUSB3KIT-003,CYUSB3ACC-005 kit) as slave fifo to connect with FPGA board.
Till now, I have successfully made data received from FPGA on USB control center. But When running BULK OUT, that is, sending data from USB to FPGA, FPGA failed to received the data.
The related results showned below.
Figure-1 show Streamer failed to transfered data. Figure-2 show FPGA trigger signal flagc_IBUF and flagd_IBUF always remaid 0, that is, flagc and flagd signals were not be sent from firmware.
Can you help us figure out the reason? We all appeciate you support.
Show Less
Hi, there
I have a file stored in SPI flash ROM, and need to transfer to the host after boot up.
I'm using two DMA channels working with end points. One is for receiving host command, the other is for data out transfer.
After command come in, the DMA callback will explain the command, read data from SPI flash and do the steps below:
CyU3PDmaChannelGetBuffer(&DCITxChHandle, &txBuffer, 0);
CyU3PMemCopy(txBuffer.buffer, (uint8_t*)TxBuffer, tx_length);
CyU3PDmaChannelCommitBuffer (&DCITxChHandle, tx_length, 0);
Now my situation is if I don't manipulate the SPI module in the callback, just transfer any data in the ram, the firmware works fine. if I want to write the flash in the callback function, no matter how many data should write to the flash, it still works fine.
But when I read data from flash and send to the host, it will stuck after certain packages. It looks like that when stuck begin, first command had been received, but the commit buffer stay in somewhere din't been sent out, and then the second command. When the third command came in, the first stuck buffer begin to really sent out, and then the 4th command came in, the second commit buffer go out, and so on.
I tried different DMA size and different DMA count, the symptoms are the same. except that large DMA size and the large count looks could transfer more correct echo data.
In callback function, I manipulate the SPI like this
if (!(aStatus & SPI_ENABLE)) // SPI Module disabled
{
aStatus &= ~DQ32_ENABLE;
aStatus |= SPI_ENABLE;
Configure_IOMatrix(aStatus);
}
spi_init();
status = hwspi_flash_read (FlashAddress, data, data_length);
CyU3PReturnStatus_t hwspi_flash_read (uint32_t addr, uint8_t* buf, uint16_t len)
{
uint8_t Command[4];
CyU3PReturnStatus_t status = CY_U3P_SUCCESS;
if (len == 0) return CY_U3P_SUCCESS;
Command[0] = 0x03; // read command
Command[1] = (addr >> 16) & 0xFF;
Command[2] = (addr >> 😎 & 0xFF;
Command[3] = addr & 0xFF;
CyU3PSpiSetSsnLine (CyFalse);
status = CyU3PSpiTransmitWords (Command, 4);
if (status == CY_U3P_SUCCESS)
status = CyU3PSpiReceiveWords (buf, len); // read data
CyU3PSpiSetSsnLine (CyTrue);
return status;
}
I trid using Events in callback and Thread to handle command explanation, so that all the procedure calling will out of the call. Don't fix the problem.
Any suggesting will welcome.
Show LessCan EZ-USB FX3 be simultaneously emulated as a video device and a serial device?
Is there an example of emulating two devices with EZ-USB FX3?
Show LessHello, which SPI Flash device can I use with CX3
Thank you, Avinoam