USB superspeed peripherals Forum Discussions

Hi,

[0] I am trying to get the CX3 to work with our own mipi camera ( RAW 8 bit 4224x3136 pixels (432 Hblank and 6236 Vblank), 108 mhz clock (so 216Mhz bit rate), 4 lanes, 2.2 fps), currently using an Econ Denebola baseboard.

I have used the eclipse tool to generate a configuration for that and merged the results with the Denebola demo code and the Cx3UvcOV5640 code present in the Cypress SDK.

Unfortunately so far the DMA callback function is not called.

Things I checked:
- If i use the camera with the exact same settings as i am using now on the devboard accompanying the camera it works (so camera is outputting something useful over the MIPI bus). Also verified the mipi bus with scope and all seems ok.

- If i enable the CyCx3AppMipiErrorThread to print the results of the CyU3PMipicsiGetErrors function i get all 0's. But if we short eg a data line the error counters go up. So i am pretty sure the MIPI block thinks it is (somewhat) working. It would be useful to have a better indication of this though.

- I also print the CyU3PMipicsiQueryIntfParams result params in the loop, these always are what i configured them to be

- If i do a CyU3PGpifGetSMState in the CyCx3AppMipiErrorThread loop, it prints that the GPIF is in state 2 all the time. Looking at cyu3mipicsi.h this corresponds to #define CX3_WAIT_FOR_FRAME_START_SCK0           2, so it seems the GPIF block never got going.

- If i use CyU3PDmaMultiChannelGetStatus i get state 2 (CY_U3P_DMA_ACTIVE) for both sockets 0 and 1 and prodXferCount = consXferCount = 0. If i check the contents of the DMA buffers then nothing changes in there (but if GPIF is not working as detected in the previous step then this is logical).

So first guess is that there is something going wrong between MIPI bus and GPIF block. Is there anything else  i can check to get a better idea what is going on there ?

Related questions:
[1] To put the gpif in pauze mode there seem to be 2 different functions
Generated code (by exclipse tool):

    /* Start the state machine. */
    status = CyU3PGpifSMStart (CX3_START_SCK0, ALPHA_CX3_START_SCK0);
        ...

    /* Pause the GPIF interface*/
    CyU3PGpifDisable(CyFalse);

Refcode:
      /* Start the state machine. */
    status = CyU3PGpifSMStart (CX3_START_SCK0, ALPHA_CX3_START_SCK0);
        ...
    /* Pause the GPIF interface*/
    CyU3PGpifSMControl(CyTrue);

    /* Resume the Fixed Function GPIF State machine */
    CyU3PGpifSMControl(CyFalse);

Is the generated code correct ? Because after the disable there is no more "start", but maybe the CyU3PGpifSMSwitch function will also reenable the gpif ? ?

[2] In the CX3 TRM it is stated
"Packing more than one pixel per PCLK is possible. For example, selecting the “MIPI CSI input -Data format"
configured as "RAW8" and the  “MIPI interface configuration  –  data format”  as a 24bit  format  (RGB888)  will
output  three pixel  data  per PCLK.  Similarly,  two 10 bit or 12bit pixels can be packed and output per PCLK
using the 24 bit output format."

But i cannot find anywhere how I can do this ?

[3] The TRM only documetns a few of the MIPI i2c accessible registers.
Can i find documentation somewhere regarding:
#define CY_U3P_MIPICSI_REG_GPIOEN   (0x0E)

#define CY_U3P_MIPICSI_REG_GPIOIN   (0x12)

#define CY_U3P_MIPICSI_REG_PHYCLKCTL   (0x56)
#define CY_U3P_MIPICSI_REG_PHYDAT0CTL  (0x58)
#define CY_U3P_MIPICSI_REG_PHYDAT1CTL  (0x5A)
#define CY_U3P_MIPICSI_REG_PHYDAT2CTL  (0x5C)
#define CY_U3P_MIPICSI_REG_PHYDAT3CTL  (0x5E)

#define CY_U3P_MIPICSI_REG_PHY_STAT    (0x62)
#define CY_U3P_MIPICSI_REG_CSI_STAT    (0x64)
#define CY_U3P_MIPICSI_REG_CSI_ERR_EN  (0x66)
#define CY_U3P_MIPICSI_REG_MDLSYN_ERR  (0x68)
#define CY_U3P_MIPICSI_REG_CSI_DID     (0x6A)
#define CY_U3P_MIPICSI_REG_CSI_DID_ERR (0x6C)
#define CY_U3P_MIPICSI_REG_CSI_PKTLEN  (0x6E)
#define CY_U3P_MIPICSI_REG_CSIRX_DPCTL (0x70)
#define CY_U3P_MIPICSI_REG_FRM_ERR_CNT (0x80)
#define CY_U3P_MIPICSI_REG_CRC_ERR_CNT (0x82)
#define CY_U3P_MIPICSI_REG_COR_ERR_CNT (0x84)
#define CY_U3P_MIPICSI_REG_HDR_ERR_CNT (0x86)
#define CY_U3P_MIPICSI_REG_EID_ERR_CNT (0x88)
#define CY_U3P_MIPICSI_REG_CTL_ERR_CNT (0x8A)
#define CY_U3P_MIPICSI_REG_SOT_ERR_CNT (0x8C)
#define CY_U3P_MIPICSI_REG_SYN_ERR_CNT (0x8E)

#define CY_U3P_MIPICSI_REG_MDL_ERR_CNT (0x90)
#define CY_U3P_MIPICSI_REG_FIFO_STAT   (0xF8)

Thanks!