USB Superspeed Peripherals

Hi,

We intend to use a camera module (sensor + FPGA) with the FX3 and UVC to the Host like in AN75779.
The module outputs VGA@60fps but has a pretty low pixel clock (20MHz).

I’m trying to check if the module timing is compatible with the GPIF state machine as described in AN75779.
I’m struggling to find information in the spec/appnote/community on the shortest horizontal and vertical blanking times or clock cycles required.

As far as I understand AN75779 GPIF state machine:

• The horizontal blanking must be at least 2 pixel clocks as everything happens within the GPIF state machine going through LINE_END_SCK0/1 state chains
• The vertical blanking must be much longer as it involves interrupt in the FX3 CPU and SW back triggering of the GPIF state machine (next to pixel clocks required to progress in the state machine).

Is my understanding correct ?
Is there a minimum time (for a given CPU clock) I can take in account for the vertical blanking?

Thanks in advance
JC

Hi, I've referred AN75779 doc to accomplish that for our project.

Now, we want to change the transmission mechanism:

1. FPGA will send out 2 type of data: image & info to FX3
2. image data uses dual socket & info data use single socket to receive
3. Use sw_pin to determine the type of the next incoming data
4. Each HREF may receives different type of data(ex: HREF1 – image, HREF2 – info, HREF3 – image…)
5. FPGA designs that each HREF data length is equal as the DMA buffer size(all are 8k)

Dummy state machine:

According to Getting Started doc, I've understood the mechanism for dual sockets yield:

The normal step behavior which use dual socket should like:

However, now, each HREF may receive different type of data. I worry it may cause Socket Linked List  conflict...

Ex: HREF1 – image, HREF2 – info, HREF3 – image, HREF4 – image

My inference step behavior:

In the step 1, load the DMA Descriptor1 on socket1(thread1). However, the next image data is received by socket0, not the expected socket1.

Q1: Will it cause the conflict as the following fig and cause crash for USB transmission?

Q2: If the answer for Q1 is yes. Can I use the commands in FW to reset Socket Linked List to avoid the conflict?CyU3PDmaMultiChannelReset(&glChHandleSlFifoPtoU);
CyU3PDmaMultiChannelSetXfer(&glChHandleSlFifoPtoU, 0, 0);
CyU3PDmaMultiChannelSetXfer(&glChHandleSlFifoPtoU, 0, 1); 

Thanks for your patience to read it. Any help will be highly appreciated!

Hello,

For my project, I'm currently using the FX3 (CYUSB3014) and looked into the SPI GPIO bit banging example as reference for the bit banging approach and given my timing requirements, it seems that we would need a delay less than a microsecond in between bits. From the looks of it, the smallest delay that can be used is with the CyU3PBusyWait (1uS). Is it possible to sample the logic levels of the GPIO pin/s with smaller delays and perform bit banging at a faster rate?

Thanks

Hi

I am developing a firmware that streams data  at 1080p@30 fps, I have  attached the parameters given I am not able to do streaming , the project is also attached , Is there any wrong configuration setting.

Thanks in Advance

Dears, I am literally stuck for many months in my project of the design of a 16-bit grayscale camera.  I got the superspeed FX3 kit and started with the example code in AN75779.  After multiple trials and errors, I see no progress at all.  In fact, I am more confused than before.  My ultimate aim is to get a 16-bit grayscale image from a sensor via FPGA, and feed it to an FX3 kit and get it streamed to a PC and use a LabVIEW program to acquire it for post-processing.  As I was lost in my way seeing multiple community posts and not much of programming skills, I would like to request your help to at least make a successful first step. 

1. I wanted to use the AN75779 as it (except for changing LV, FV, nRST pin numbers in GPIF)  is so I do not add any error to the original program.  I interfaced it with a DeoNano FPGA board with a custom made interface board.  I changed the pin numbers in GPIF accordingly.  Please see GPIF interface definition picture attached.  I use VLC to try to get some video.  I wrote a test program in FPGA/verilog to generate the PCLK, LV, FV, DATA.  I start with 8 bit DATA as in GPIF the original program it was 8 bit.  Some Signaltap plots of FV, LV shown.  I made it for 1280 x 720, 30FPS using PCLK of 48MHz.  I added Frame and Line blanking accordingly so that the final frame rate is 30FPS.  I uncommented the DEBUG_PRINT_FRAME_COUNT in uvc.h as per suggestion from other posts.  But I always get Frame timer overflow and 0 frames and 0 buffers in the UART debug as attached.  Is my idea/attempt wrong?  I tried giving both longer and shorter blanking times keeping the 30FPS more or less same.  If I manage to make this work, I hope I can make some progress to my actual project goal.

2. I am not using any I2C lines for now.  Will this work without I2C connected?  I guess so.

If I manage to get this FV, LV, Data test signal correctly, I will be making the actual readout in same sequence and timing hoping it to work fine.  Later I will have to change the resolution too as I have one QVGA and one VGA sensors to be interfaced individually.

Thank you for your kind help.

Regards

I'm feeling a little out of my depth here as I'm a System Administrator rather than a seasoned Electronics Engineer, I hope this question makes sense...

I am trying to upgrade two machines, that each have several Cypress Westbrige devices attached to them, from Ubuntu 16.04 to Ubuntu 20.04. With Ubuntu 16.04, all devices enumerate correctly first as 04b4:00f3 and then go on to download their custom firmware, detach and reattach. However, with 20.04 I get the following errors:

Feb 23 12:05:47 master kernel: usb 1-6-port1: status 0101, change 0000, 12 Mb/s
Feb 23 12:05:47 master kernel: usb 1-6-port1: indicator auto status 0
Feb 23 12:05:47 master kernel: usb 1-6.1: new full-speed USB device number 3 using xhci_hcd
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:47 master kernel: usb 1-6.1: new full-speed USB device number 4 using xhci_hcd
Feb 23 12:05:47 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:48 master kernel: usb 1-6.1: device descriptor read/64, error -32
Feb 23 12:05:48 master kernel: usb 1-6-port1: attempt power cycle
Feb 23 12:05:48 master kernel: usb 1-6-port1: not enabled, trying reset again...
Feb 23 12:05:48 master kernel: usb 1-6.1: new full-speed USB device number 5 using xhci_hcd
Feb 23 12:05:48 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:48 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: device not accepting address 5, error -71
Feb 23 12:05:49 master kernel: usb 1-6.1: new full-speed USB device number 6 using xhci_hcd
Feb 23 12:05:49 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: Device not responding to setup address.
Feb 23 12:05:49 master kernel: usb 1-6.1: device not accepting address 6, error -71
Feb 23 12:05:49 master kernel: usb 1-6-port1: unable to enumerate USB device

Two other similar devices connected to this machine at 1-6.3 and 1-6.4 show identical errors.

I have tried:

• using 'uhubctl' to power cycle the ports of the 1-6 hub
• using 'uhubctl' to reset each of the ports on the hub
• adding the 'usbcore.autosuspend=-1' kernel parameter (after reading your KBA222372 - Trouble Shooting Guide for the FX3/FX3S/CX3 Enumeration)
• adding extra time for the device descriptor read with kernel parameter 'usbcore.initial_descriptor_timeout=10000' (10s rather than the default 5s)
• setting various combinations of 'usbcore.use_both_schemes' and 'usbcore.old_scheme_first' to change method the kernel uses to initialise USB device

Have any other users experienced similar problems Cypress FX3 based devices when running Ubuntu 20.04?

Thx

Hi, 

I made my custom board(FX3 and Camera Module).

I connected it and wrote my custom source code.

The black screen was printed in AMCAP, so I checked the debug message with wireshark.

The Wireshark confirmed that the data was output.

The resolution is 340(W) x 260(H), 30fps and 12bit data output.

You can see data in wireshark log.

• wireshark log  => ((16380 * 10) + 13292=177,092     
• resolution  =>  340*260*2 = 176,800
• difference => 177,092 - 176,800 = 292
• As above, additional buffers are entered, and it is necessary to check if there is a problem with the code.

I tried to change DMA Buffer size(CY_FX_EP_BULK_VIDEO_PKT_SIZE and CY_FX_EP_BULK_VIDEO_PKTS_COUNT ) in uvc.h

If i change buffer size, the buffers in the data packet are output differently.

Regards,

Jay

你好，我使用一个uvc工具验证发送设置camera 图像对比度，饱和度命令，但是CyU3PUsbRegisterSetupCallback(CyCx3AppUSBSetupCB, CyTrue)注册的回调函数不响应，函数头里加了日志也没有通过串口打印出来。此uvc工具直接测试usb camera摄像头是有效果的。我想咨询一下，fx3需要如何注册回调函数才会响应类似命令？