USB superspeed peripherals Forum Discussions
Hello,
I am using JLINK BASE with cypress EZ USB sdk .I am getting ERROR: Bad JTAG communication: Write to IR: Expected 0x1, got 0x7 (TAP Command : 15) @ Off 0x1157.
why this eeror ?I am not able to do debug the program.
for some application,it will not thrown ERROR: Bad JTAG communication: Write to IR: Expected 0x1, got 0x7 (TAP Command : 15) @ Off 0x1157.
but it will show starting target cpu..(as shown in the attached snap).after this,there is further debug(there is no further stepover option).help me.
thank you.
Show LessI want to get the system tick in millisecond, which function can get it?
when debug message output is OK, then use CyU3PTimerCreate to create one timer, use CyU3PDebugPrint in timer call back function, It can not print message in call back function, I have confirm the timer call back have execute, in call back function increase one value, I have see this value increase when time elapse.
Show LessHello,
I'm trying to send raw Image data with my CYUSB3KIT-003 to my PC. However currently it looks like my program to send the data is to slow (I get 2 Byte with 72MHz). My program is similar to the AN75779 example except, with out UVC. Since i have problem with my program, i tried to modify AN75779 example, but i don't finde the code part ,where the USB-Connection is defined as UVC connection. What should i delete?
kind regards,
Matthias
Show LessHello,
I am using the EZ USB FX3 board to build an interface to an external device that requires an approx. 100MHz clock and puts out a serial 100MHz serial output data stream.
In order to make the interface work, I need the FX3 to generate 2 approx. 100MHz output clocks, with adjustable phase difference.
I use the FX3 PCLK as a master clock running at approx 100MHz. That works fine.
Now I want to generate a second output clock signal, at the same frequency, but with controllable phase shift w.r.t. PCLK by using an FX3 internal DLL (delay locked loop).
I managed to generate the 2nd clock signal on a GPIO pin by using complex gpio, in PWM mode, and setting period and duty cycle with period and threshold ticks.
I am also able to change its phase with respect to the PCLK by using an FX3 DLL.
However, it seems that PWM period settings smaller than 8 have no effect on the period of the PWM signal. I was not able to get a 100MHz gpio complex output signal,
also not by decreasing fast clock div value. At best I got approx. 25MHz.
I found out that this was confirmed in one of the entries in the developer community as a bug in the FX3 chip with PWM period settings smaller than 8.
I have a few questions:
- are there (newer) versions of the FX3 where this minimal PWM period bug has been fixed?
- are there alternative ways, other than complex gpio, that allow for generating 2 100MHz output clocks with adjustable phase relation?
I did read about the SDIO interface with S0 & S1 ports that talk about the ability to generate 100MHz clocks, and with a seperate DLL, which is "recommended not to use"
in the technical manual. Is it possible to use these to generate a steady 100MHz clock with adjustable phase, without actually implementing a full SDIO interface?
Any help is appreciated,
Best regards
Show LessHi Cypress,
We using CYUSB3KIT-003 development kit to test the "cyfxisosrcsink" firmware project, and attachd we encounter abnormal data streaming while the device (CYUSB3KIT) connect to Orico PVU3-2O2I extension card.
Orico was NG
The issues seems link to we tested USB3-IF compliance before (Fresco extension card), Could you please confirm how to resolve this issues ASAP, thanks.
Renesas was OK (72MHz)
BRs
Show LessHi there,
When I was reviewing source code for FX3 U3V device, I found a question as below:
the function source code is:
===
uint32_t *uniqueIDreg = (uint32_t *)0xE0055010;
void CyFxU3VUpdateSerialNum(void)
{
uint8_t j=0;
uniqueIDL = *(uniqueIDreg);
uniqueIDH = *(uniqueIDreg+32);
for(j=0; j<4; j++)
{
CyU3VABRM[260+j] = ((uniqueIDL>>(j*8))&0x000000FF);
CyU3VABRM[264+j] = ((uniqueIDH>>(j*8))&0x000000FF);
}
}
===
It is to update the unique ID serial number from register whose address is 0xE0055010.
But!
uint8_t CyU3VABRM[528] =
{
0x00, 0x00, 0x01, 0x00, // GenCP Version: Minor version (16bits) = 0x0000 , Major version (16bits) = 0x0001
U3V_MANUFACTURER_NAME, // Manufacturer Name String in ASCII, 64 bytes
U3V_MODEL_NAME, // Model Name String in ASCII, 64 bytes
U3V_FAMILY_NAME, // Family Name string in ASCII, 64 bytes
U3V_DEVICE_VERSION, // Device Version String in ASCII, 64 bytes
NULL_64, // Manufacturer info string, 64 bytes, NULL <-----------------Wrong! CyU3VABRM[260+0] begins here!!!
NULL_64, // Serial Number string, 64 bytes, to be filled during runtime by CyFxU3VUpdateSerialNum()
How this happens?
BTW, could anyone tell me a fake 8-byte unique ID serial number to test? The host seems stall after the 8-byte data received.
Or could help provide the dump data of these sequence?
Tks so much!!!
Show LessImport project “C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\firmware\msc_examples\cyfxmscdemo”, then select build project, appear following error message.
08:43:36 **** Build of configuration Default for project USBMassStorageDemo ****
make all
Cannot run program "make" (in directory "C:\Users\peter\Desktop\temp\EZ-USB\FW\USBMassStorageDemo"): CreateProcess error=2, The system cannot find the file specified
Error: Program "make" not found in PATH
PATH=
08:43:36 Build Finished (took 12ms)
Show LessHey there,
Since more than ten years were using a CY7C68013 USB without any big problems. However, we recently noticed customer increasing complaining about several "USB-Connection Failures". Therefore, we now intensely are trying to fix the issues. I updated the Cypress driver to the newest version and removed several issues in our Code. However also noticed that some errors were CPU load depended. When having a low CPU loads USB data traffic get damaged since we only have a small buffer on our FPGA. When increasing the CPU load with a CPU benchmarking tool no data loss is visible. After some research I found the following Discussions:
FX3 bulk transfer unreliable on Windows 10
Cyusb3 v1.2.3.20 load depending data lost issue?
FX3 Bulk Transfer gaps on fast Windows 10 laptops
Thereafter I disable the C-States in the BIOS setting and no data loss was visible. Since several thousand installed were made on different computers, disable de C state in the BIOS is not an option. Neither adding a dummy thread to our application. Therefore, I may have to add a dummy endpoint as mentioned in the discussion. Or is there any other solution for that problem?
Regards
Yves
Show Less