USB superspeed peripherals Forum Discussions
AN75779 need an image sensor with the following features :
8-bit synchronous parallel data interface
16 bits per pixel
YUY2 color space
1280 x 720-pixel resolution (720p)
Some image sensors do not meet the requirements (such as OV2710) . only support for output formats: RAW RGB .
How to modify AN75779 in order to this image sensors.
Or do we have other Solution for this image sensors ?
I designed GPIF as an Async SRAM interface.
No PACKET-related pins were assigned.
GPIF is a 16-bit data interface.
How should I write 8-bit data below?
if rqtCode = 0x01, Params[0] = 0x02, Params[1] = 0x03, Params[2] = 0x04, Params[3] = 0x05, Params[4] = 0x06, Params[5] = 0x07, Params[6] = 0x08,
Is it correct to write 16-bit Data in the first 0x0102, second 0x0304, Third 0x0506, fourth 0x0708 order?
Does the s-port automatically save to memory when 8 data are entered?
Enter 0x06 in rqtCode,
and aaa[0] to [7] should be insert data to store in eMMC memory?
The eMMC memory has no response from the Clock and Data pins.
/* Break the request data into bytes. */ rqtCode = CY_U3P_DWORD_GET_BYTE3 (fxAppMbox.w0); /* The request code is the MSB of w0. */ params[0] = CY_U3P_DWORD_GET_BYTE2 (fxAppMbox.w0); params[1] = CY_U3P_DWORD_GET_BYTE1 (fxAppMbox.w0); params[2] = CY_U3P_DWORD_GET_BYTE0 (fxAppMbox.w0); params[3] = CY_U3P_DWORD_GET_BYTE3 (fxAppMbox.w1); params[4] = CY_U3P_DWORD_GET_BYTE2 (fxAppMbox.w1); params[5] = CY_U3P_DWORD_GET_BYTE1 (fxAppMbox.w1); params[6] = CY_U3P_DWORD_GET_BYTE0 (fxAppMbox.w1); |
case CYFXSTORRQT_QUERYDEV: { CyU3PSibDevInfo_t devInfo; status = CyU3PSibQueryDevice (params[0], &devInfo); if (status == CY_U3P_SUCCESS) { /* Only some of the device info fields are being returned here, so as to restrict the response to 8 bytes. This can be expanded by breaking up the response into multiple messages. */ rspMbox.w0 = CY_U3P_MAKEDWORD (CYFXSTORRESP_DEVDATA, (uint8_t)devInfo.cardType, (uint8_t)devInfo.numUnits, (uint8_t)devInfo.writeable); rspMbox.w1 = (uint32_t)devInfo.blkLen; fxAppDevBlkSize = devInfo.blkLen; } else { rspMbox.w0 = (CYFXSTORRESP_STATUS << 24) | status; rspMbox.w1 = 0; } CyU3PMboxWrite (&rspMbox); } break; case CYFXSTORRQT_QUERYUNIT: { CyU3PSibLunInfo_t unitInfo; status = CyU3PSibQueryUnit (params[0], params[1], &unitInfo); if (status == CY_U3P_SUCCESS) { /* Only some of the device info fields are being returned here, so as to restrict the response to 8 bytes. This can be expanded by breaking up the response into multiple messages. */ rspMbox.w0 = CY_U3P_MAKEDWORD (CYFXSTORRESP_UNITDATA, (uint8_t)unitInfo.valid, (uint8_t)unitInfo.location, (uint8_t)unitInfo.type); rspMbox.w1 = unitInfo.numBlocks; } else { rspMbox.w0 = (CYFXSTORRESP_STATUS << 24) | status; rspMbox.w1 = 0; } CyU3PMboxWrite (&rspMbox); } break; case CYFXSTORRQT_READ: { uint32_t flag; status = CyU3PDmaChannelSetXfer (&fxAppReadChannel, params[3] * fxAppDevBlkSize); if (status == CY_U3P_SUCCESS) { status = CyU3PSibReadWriteRequest (CyTrue, params[0], params[1], params[2], fxAppMbox.w1, CYFXSTORAPP_SIB_RDSOCK); if (status == CY_U3P_SUCCESS) { status = CyU3PEventGet (&fxAppEvent, CYFXAPP_SIB_DONE_EVENT, CYU3P_EVENT_OR_CLEAR, &flag, CYFXSTORAPP_XFER_TIMEOUT); if (status == CY_U3P_SUCCESS) { if (fxAppXferStatus == CY_U3P_SUCCESS) { status = CyU3PDmaChannelWaitForCompletion (&fxAppReadChannel, CYFXSTORAPP_XFER_TIMEOUT); } else status = fxAppXferStatus; } if (status != CY_U3P_SUCCESS) { CyU3PSibAbortRequest (params[0]); CyU3PDmaChannelReset (&fxAppReadChannel); } } } rspMbox.w0 = (CYFXSTORRESP_STATUS << 24) | status; rspMbox.w1 = 0; CyU3PMboxWrite (&rspMbox); } break; case CYFXSTORRQT_WRITE: { uint32_t flag; status = CyU3PDmaChannelSetXfer (&fxAppWriteChannel, params[3] * fxAppDevBlkSize); if (status == CY_U3P_SUCCESS) { status = CyU3PSibReadWriteRequest (CyFalse, params[0], params[1], params[2], fxAppMbox.w1, CYFXSTORAPP_SIB_WRSOCK); if (status == CY_U3P_SUCCESS) { status = CyU3PEventGet (&fxAppEvent, CYFXAPP_SIB_DONE_EVENT, CYU3P_EVENT_OR_CLEAR, &flag, CYFXSTORAPP_XFER_TIMEOUT); if (status == CY_U3P_SUCCESS) { if (fxAppXferStatus == CY_U3P_SUCCESS) { status = CyU3PDmaChannelWaitForCompletion (&fxAppWriteChannel, CYFXSTORAPP_XFER_TIMEOUT); } else status = fxAppXferStatus; } if (status != CY_U3P_SUCCESS) { CyU3PSibAbortRequest (params[0]); CyU3PDmaChannelReset (&fxAppWriteChannel); } } } rspMbox.w0 = (CYFXSTORRESP_STATUS << 24) | status; rspMbox.w1 = 0; CyU3PMboxWrite (&rspMbox); } break; case CYFXSTORRQT_ECHO: { rspMbox.w0 = (CYFXSTORRESP_ECHO << 24) | (fxAppMbox.w0 & 0xFFFFFF); rspMbox.w1 = fxAppMbox.w1; CyU3PMboxWrite (&rspMbox); } break; default: { /* Unsupported command. */ rspMbox.w0 = (CYFXSTORRESP_STATUS << 24) | CY_U3P_ERROR_CMD_NOT_SUPPORTED; rspMbox.w1 = 0; CyU3PMboxWrite (&rspMbox); } break; } |
What is GPIO state of FX3 after it is loaded with slave fifo example(AN65947)? I observe GPIO 50 and 52 are not tristated. I connect these pins to other device. They should be tristated when loaded with this firmware. The default states are tristated, but after booting with slave fifo example,32 bits mode, they are NOT traistated.Why?
Thank you.
Show LessHi,
Is there a way to check how many memory is left for dma buffers in CX3 codes ?
I'm experiencing a weird behavior with CyU3PMultiChannelDestroy, returning an error code 16 (memory).
I would rather expect this to happen at creation of dma channel, not at deletion... However after I reach this error code, there is no way to get dma creation working after.
So second question is : do you have a snippet code for resetting completly the dma memory buffer ?
Thank you for your help,
best regards.
Show LessIn my PCB, FX3's IO power rail is set to 1.8V, which is also the power rail for FX3's JTAG interface. But problem occurs when openning segger GDB server, its GUI disappear. I think the voltage may be too low for the dongle to recognize the PCB. Is it true? Thank you.
Show LessDear Sir:
We have a USB dongle application, it used for Mpeg2 TS stream transport.
However, it used 3 Bulk endpoint and 2 INT endpoint as my attachment shows. with EP6/EP1-OUT for I2C Write, EP8/EP1-IN for I2C Read, Our local Agent told us they did not have any experience for this Endpoint Configuration of USB dongle application, and they said it may not sucess.
So would you please let me know if the Endpoint configuration is suit for USB dongle application ?
Besides, do i need to open 2 Thread for 3 Bulk application, 1 for I2C Write/read, 1 for TS Dump?
We appreciate your help
Show LessI use FX3 to configure xilinx Kintex-7 FPGA. I uses the cypress example firmware of one application note that uses FX3 to configure xilinx FPGA in slave serial mode. The configuration data is a 15MB bin file. The configure is unsuccessful. I use JTAG to debug the firmware and find that the FX3 only get 7MB data. The firmware fails to fill the buffer when it want to get more data. Is that because the configuration data is huge that exceeds the RAM of FX3? How to resolve to problem. Thank you.
Show LessHello,
I have a board with an FX3 connected to an FPGA where the GPIF is the synchronous master mode. I am not planning on using any address lines so I'm kind of confused about how to use threads and sockets. My main goal is to read several USB3 packets worth of data at a time from the GPIF using IN_DATA and send them over USB. Is it alright if I only use one thread, and one consumer and one producer socket? Is there an advantage to use more threads and sockets?
Looking at the slfifosync example, I see that PIB_SOCKET_0 was selected as the producer and PIB_SOCKET_3 was selected as the consumer. I'm actually pretty uncertain about threads and sockets, even though I've read all of the documentation in the FX3API guide, watched the video tutorials, and read the appnotes.
What exactly are DMA threads? Are these the same threads that are created by the C API function, CyU3PThreadCreate()? When would you use multiple threads and why? And when would you use multiple sockets and why?
What physical meaning do these thread and socket numbers have, do they come from what is placed on the bus during an IN_ADDR action?
Show LessI'm not sure how to configure the MIPI Receiver for the CX3.
My camera is the OV7251. It has a resolution of 640x480 at 120FPS and 10-bit monochrome raw pixels. 1 MIP lane.
1. What should the values of V and H blanking be? nothing about blanking is mentioned in the datasheet of the image sensor.
2. What should be the values of THS Prepare and Zero?
3. Do I have to set the CSI Clock value to the *exact* correct value? What if the image sensor clock is not exactly correct?
4. Should my Output pixel clock equal 36,864,000 (640x480x120) ?
5. What should be the Fifo delay?
6. Is there somewhere a document that explains all of this? I have read several Cypress documents, including the FX3 and CX3 TRMs, and the AN75779 and AN90369, but they didn't seem to help me find the answers.
Many thanks
Hugo
Show LessHi,
For our application, we need GPIF 32 bit for communicating between FX3 and Artix7 FPGA. A design was made in GPIFII designer following AN75779 as we need UVC for streaming video from a camera sensor. In GPIFII designer, interface was changed to 32 bit and LD_DATA_COUNT and LD_ADDR_COUNT was adjusted as per instructions mentioned in the datasheet. We have attached the GPIFII designer project for perusal. It would be great if someone can confirm whether the project and files generated are correct.
We were getting errors in DMA channel commit. While changing to 32bit implementation, we have modified the following.
- /* UVC Probe Control Settings for a USB 3.0 connection. */
uint8_t glProbeCtrl[CY_FX_UVC_MAX_PROBE_SETTING] = { 0x00, 0x00, /* bmHint : no hit */
0x01, /* Use 1st Video format index */
0x01, /* Use 1st Video frame index */
0x0A, 0x8B, 0x02, 0x00, /* Desired frame interval in the unit of 100ns: 60 fps */
0x00, 0x00, /* Key frame rate in key frame/video frame units: only applicable
to video streaming with adjustable compression parameters */
0x00, 0x00, /* PFrame rate in PFrame / key frame units: only applicable to
video streaming with adjustable compression parameters */
0x00, 0x00, /* Compression quality control: only applicable to video streaming
with adjustable compression parameters */
0x00, 0x00, /* Window size for average bit rate: only applicable to video
streaming with adjustable compression parameters */
0x00, 0x00, /* Internal video streaming i/f latency in ms */
//OPENCV
0xF0, 0xF9, 0x2C, 0x00, /* Max video frame size in bytes */
0x00, 0x78, 0x00, 0x00 /* No. of bytes device can rx in single payload = 30 KB */
};
/* UVC Probe Control Setting for a USB 2.0 connection. */
uint8_t glProbeCtrl20[CY_FX_UVC_MAX_PROBE_SETTING] = { 0x00, 0x00, /* bmHint : no hit */
0x01, /* Use 1st Video format index */
0x01, /* Use 1st Video frame index */
0x0A, 0x8B, 0x02, 0x00, /* Desired frame interval in the unit of 100ns: 15 fps */
0x00, 0x00, /* Key frame rate in key frame/video frame units: only applicable
to video streaming with adjustable compression parameters */
0x00, 0x00, /* PFrame rate in PFrame / key frame units: only applicable to
video streaming with adjustable compression parameters */
0x00, 0x00, /* Compression quality control: only applicable to video streaming
with adjustable compression parameters */
0x00, 0x00, /* Window size for average bit rate: only applicable to video
streaming with adjustable compression parameters */
0x00, 0x00, /* Internal video streaming i/f latency in ms */
// OPENCV.
0xF0, 0xF9, 0x2C, 0x00, /* Max video frame size in bytes */
0x00, 0x78, 0x00, 0x00 /* No. of bytes device can rx in single payload =30KB */
};
- /* UVC Video Streaming Endpoint Packet Size */
#define CY_FX_EP_BULK_VIDEO_PKT_SIZE (0x400) /* 1024 Bytes */
/* UVC Video Streaming Endpoint Packet Count */
#define CY_FX_EP_BULK_VIDEO_PKTS_COUNT (0x1E) /* 16 packets (burst of 16) per DMA buffer. */
/* DMA buffer size used for video streaming. */
#define CY_FX_UVC_STREAM_BUF_SIZE (CY_FX_EP_BULK_VIDEO_PKTS_COUNT * CY_FX_EP_BULK_VIDEO_PKT_SIZE) /* 16 KB */
/* Maximum video data that can be accommodated in one DMA buffer. */
#define CY_FX_UVC_BUF_FULL_SIZE (CY_FX_UVC_STREAM_BUF_SIZE - 16)
/* Number of DMA buffers per GPIF DMA thread. */
#define CY_FX_UVC_STREAM_BUF_COUNT (4)
- DQ32bit is set to true, SPI is disabled
is there any change we need to make in DMA width or something to get successful transactions or CY_U3P_PIB_GPIF_BUS_CONFIG field
Show Less