USB superspeed peripherals Forum Discussions
Hi All,
Can someone point me to documentation for the CX3's I2C controller. Specifically, I am seeing one of the I2C chips on my bus not releasing SDA on power-up. My hunch is if I clock SDA a few times it would release, but I don't know how to access the signals independently of the I2C controller in the CX3. I don't see GPIO numbers for controlling the I2C signals independently of the controller.
Thanks,
Scott
Show LessI used cyusb314 in slavefifo mode with 16bits bus, and there are two bulk endpoints(0x81 0x01) in it. the dma buffer size corresponding each endpoint is 16*1024 bytes, and the counter of each dma buffer is 2, the pclk is internal(96MHz). The fpga drive the slavefifo bus in negedge pclk. There ar some srange problems about the slavefifo mode.
(1) While I transfer data from fpga to cyusb3014(in diection), the slwr should be last 8193 pclk cycles(in word), then the transfered data are right. If the slwr last 8192 pclk cycles, the data still be right(the counter of in dma buffer must be 2), but if i changed the the counter of in dma buffer like 4, the cyusb3014 will be disconnect when i transfer data from fpga to cyusb3014. you can see the sequence diagram in fig1 and fig2(the slwr last 8193 pclk cycles, and the 4 counter of in dma buffer is ok).
(2) While I transfer data from cyusb3014 to fpga, the transfered datas are correct. if the transfered datas are no more than 256(in word), the data will be transfered only once, the flagc will be 1, and then i can capture the sequence diagram like fig3, but if transfered datas more than 256(like 4096 word), the data must be transfered twice, then the flagc will be 1, and the sequence diagram will be captured like fig4 ,fig5 and fig6, and you can see the counter of captured datas is 8192(in word), why?
(3) In out direction, while the sloe and slrd are 0 after the counter of 1(fig4), the vaild data will be read at the counter 6(posedge pclk), the pdf of cyusb3014 points that the delay of sloe(slrd) and the bus data is 2 pclk cycles, while i find that the delay in my design is 3( the bus data at the counter 2 3 4 is 0), why?
(4) I used some gpio pins in the firmware to control fpga, while i find that the enumeration time of cyusb3014 is too long(it looks like 8-9 seconds), if the firmware is programed in 24AA1025. Is that normal? you can see my firmware in appendix.
fig 1
fig 2
fig 3
fig 4
fig 5
fig 6
Show LessHi Srinath S_16
I used cyusb314 in slavefifo mode with 16bits bus, and there are two bulk endpoints(0x81 0x01) in it. the dma buffer size corresponding each endpoint is 16*1024 bytes, and the counter of each dma buffer is 2, the pclk is internal(96MHz). The fpga drive the slavefifo bus in negedge pclk. There ar some srange problems about the slavefifo mode.
(1) While I transfer data from fpga to cyusb3014(in diection), the slwr should be last 8193 pclk cycles(in word), then the transfered data are right. If the slwr last 8192 pclk cycles, the data still be right(the counter of in dma buffer must be 2), but if i changed the the counter of in dma buffer like 4, the cyusb3014 will be disconnect when i transfer data from fpga to cyusb3014. you can see the sequence diagram in fig1 and fig2(the slwr last 8193 pclk cycles, and the 4 counter of in dma buffer is ok).
(2) While I transfer data from cyusb3014 to fpga, the transfered datas are correct. if the transfered datas are no more than 256(in word), the data will be transfered only once, the flagc will be 1, and then i can capture the sequence diagram like fig3, but if transfered datas more than 256(like 4096 word), the data must be transfered twice, then the flagc will be 1, and the sequence diagram will be captured like fig4 ,fig5 and fig6, and you can see the counter of captured datas is 8192(in word), why?
(3) In out direction, while the sloe and slrd are 0 after the counter of 1(fig4), the vaild data will be read at the counter 6(posedge pclk), the pdf of cyusb3014 points that the delay of sloe(slrd) and the bus data is 2 pclk cycles, while i find that the delay in my design is 3( the bus data at the counter 2 3 4 is 0), why?
(4) I used some gpio pins in the firmware to control fpga, while i find that the enumeration time of cyusb3014 is too long(it looks like 8-9 seconds), if the firmware is programed in 24AA1025. Is that normal? you can see my firmware in appendix.
fig 1
fig 2
fig 3
fig 4
fig 5
fig 6
Query 1 that i talk about is my fault, fig 1 and fig 2 are the transfer from FPGA to FX3, If the DMA buffer is 16384 bytes, the FPGA should send 8192 words to FX3, not 8193, but if i put the counter of DMA buffer into 4 or more, the usb chip will be disconnected itself, when the transfer from FPGA to FX3 is done.(#define CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U (4)//in)
Query 2 is said that If i send no more than 256 words from pc through FX3 to FPGA, the transfer will be correctly, and the 256words will be sent only once from FX3 to FPGA, then FPGA chipscope will capture the flagc active(1, the out dma buffer is not empty); while if i send data more than 256words from fx3 to FPGA, then FPGA chipscope will not capture the flagc active(1, the out dma buffer is not empty) until the data is sent from fx3 to fpga the second time, and the fpga chipscope will capture double data, you can see it in fig 6(ie i send 4096 words from fx3 to FPGA, the fpga will not capture data until the data is sent the second time //CY_FX_SLFIFO_DMA_BUF_COUNT_U_2_P (2)). fig 3 and fig4 is the transfer from fx3 to fpga, the counter of data is 16 words, and the data will be set only once. Fig 5 is the partial magnification of fig6, and you can see that the counter of captured data is 8192 words(the counter of data transfered from fx3 to fpga is 4096 words).
、Fig3~fig 6 are the IN transfer.
Query 4 is said that when the cyub3014 powers on, then the firmware is load from EEPROM to cyusb3014, i will not see the enumerated device in device list until the enumeration is completed, and the duration is 8-9s. Is that normal?
The GPIF II state machine file is in appendix.
Show LessIf it’s possible to run a debug session into an RTOS; on the AVC code that accompanies AN75779, what’s the process to get past the first couple instructions in Main then follow function call CyU3PKernelEntry into the ThreadX RTOS?
As soon as the code gets out of Main, I can no longer seem to track it. Any help is appreciated.
Steps:
- Copy and unzip AN75779.zip and AN75779 How to Implement guide to PC
- Connect two USB connectors on CYUSB3KIT-003 to two USB ports on PC
- Start TeraTerm & Setup as Serial Port to new Com Port at 115200 baud
- Start Cypress’ EZ USB Suite
- Import AN75779 project UVC
- Build UVC_AN75779 project – select “Debug(Debug Configuration)”
- Set Debug Configuration for UVC_AN75779 project
- Select GDB OpenOCD Debugging
- Leave Main tab untouched
- On Debugger tab, ensure
- Executable = C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\JTAG\OpenOCD\Windows\openocd.exe
- Config options = -f "C:\Program Files (x86)\Cypress\EZ-USB FX3 SDK\1.3\JTAG\OpenOCD\Config\arm926ejs_fx3.cfg"
- On Starup tab, de-select “Enable ARM semihosting” and “Pre-run reset”
- Select “Apply” then “Debug”
- Notice when progress bar in lower right corner completes uvc.c fills center window with first command in main highlighted.
At this point, I don’t foresee where the code’s going so I decide to step over and into – but get lost after CyU3PKernelEntry command. ???
Main
CyU3PDeviceInit <– Step Over
CyU3PDeviceCacheControl <– Step Over
CyU3PDeviceConfigureIOMatrix <– Step Over
Dozen io_cfg settings <– Step Over each one
- CyU3PKernelEntry <-- I don’t know how to debug at this point. Resuming or stepping into causes program to run, a window for 0x0 pops up over the uvc.c window with red text, “No source available for “0x0”
- [View Disassembly…] <-- clicking on this radio button opens a Disassembly window that shows address lines for code followed by the text, “Unable to retrieve disassembly data from backend.”
and Tera Term displays the following output:
Error: Reading Sensor ID failed!
UsbEventCB: Detected SS USB Connection
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
USBSetupCB:In SET_FTR 0::1
UsbEventCB: SUSPEND encountered...
Entering USB Susp
Notes:
- Code does appear to be halted @ fffffff8, which is highlighted green in the Disassembly window.
- ‘Step Return’ causes information in the Console to update and the Disassembly code to refresh.
- ‘Step Into’ and ‘Step Over’ appear to have no effect.
-------------
I did find some existing posts and attempted various modifications with no success:
A) UVC Troubleshooting Guide – KBA226722 @ https://community.cypress.com/docs/DOC-17227 appears to be related to a running application. It’s possible the code locks up without a data stream.
B) I uncommented the #define USB_DEBUG_INTERFACE line in uvc.h then ran a build then the debugger.
- There isn’t any additional output, which makes sense as the code didn’t go to area where the Debug comments are located.
C) There is a section in the readme.txt file in the UVC_AN75779 directory:
4. Updating to a new FX3 SDK version:
-------------------------------------
The cyfxtx.c and cyfx_gcc_startup.S files used here are taken from the FX3 SDK release. This version of the application makes use of FX3 SDK release version 1.3.3.
When updating the application to work with a new SDK version, you need to copy the latest cyfxtx.c and cyfx_gcc_startup.S files from the new SDK into this project. You will also need to follow the instructions for porting to the new SDK that are included in the "Getting started with the FX3 SDK" document.
Looking at copies of cyfxtx.c and cyfx_gcc_startup.S files in EZ USB SDK files and UVC_AN75779, I see no difference.
D1) Mention of running Profile Debug for RTOS in response to Community Post “debug and release mode” @ https://community.cypress.com/message/156326. I’ll try it.
- Re-build using Profile Debug option
- Change C/C++ Application in Main tab of Debug configuration by using [Search Project…] button and selecting Profile version.
- No difference
D2) More information on Profile Debug in the post “Profiling support of ThreadX” @ https://community.cypress.com/community/usb/usb-superspeed-peripherals/blog/2018/12/23/profiling-support-of-threadx
- Still no difference in my inability to follow debug after start of RTOS
Hi,
I have a simple application that FPGA(Master) keep sending data to FX3(Slave) @12.5Mhz.
Data could be seen by running similar <gpiftousb> sample, all I need to do right now is to add CLK signal and change GPIF as slave for synchronization.
I modified the original GPIFII configuration as below:
State machine configuration remains unchanged:
And copied the new header file to original firmware project, nothing else changed.
Right now I can only read 16K data for 8 times: (Match with the 4 x 32K DMA buffers), then error will occur.
By printing the state machine status from UART port,
I could see it starts from 0(START), and jumps to 1(DMAWAIT), then to 2(READDATA), and back to 1(DMAWAIT), which seems reasonable,
but the problem is it always stuck as 1(DMAWAIT) after this and will never go back to 2(READDATA), even after the PC has read out all the data from the buffer,
Looks like the DMA_RDY_TH0 flag does not go high again as it supposed to.
It's there anything else needed to be configured or any suggestions? Thanks in advance!
Best Regards,
Kevin
Show LessIn AN84868, the Fx3 switch to slave fifo mode when it completes the configuration of FPGA. In my FPGA application, after configuration the FPGA does not transfer data with FX3. The FPGA requires FX3 to send it a trigger signal and read back its response. It needs 3 GPIOs in total (2 pins for response) . I define them to GPIO(0, 1, 2) according to hardware connection. I develop my firmware based on that of AN84868. I should free these GPIO from slave fifo interface, so that it can be used as GPIO. I should remove slave fifo function in AN84868. I find in GPIF designer that I have to choose master interface or slave interface. Both are not my desired option. I only hope to choose GPIO. Can you help?
Thank you.
Show LessHi,
I used my oscilloscope to sample the MIPI data line on an OV7251 camera. The camera has a resolution of 640x480, 8 bits per pixel, and is transmitting at 60fps. It looks like it's using a MIPI clock of 400MHz, and has 1 data lane.
How should I configure CX3 MIPI Receiver?
1. Does the H-Blanking period refer to the 23.15us "no data" period between the individual lines? In my example they are nearly three times longer than the active period!
2. Does the V-blanking period refer to the 1.32ms period between the 15.34ms active frame time?
3. Do I set the H-Blanking period to 23.15/8.52 * 640 ?
4. Do I set the V-Blanking period to 1.32/15.34 * 480 ?
5. Presumably I set the CSI clock to 400MHz?
6. Do I set the Pixel clock to more than (640+1740) x (480+42) x 60 ( = 74.54MHz)
Many thanks
Hugo
Show Less
When calculating all of the timings in the MIPI receiver configurator, the CSI clock seems to be calculated as:
V-Total x H-Total x FPS x bitsperpixel
E.G. with 640 x 480 x 60fps x 8bits, with 1 lane, the CSI clock is calculated to be 73.73MHz exactly.
This seems surprising, as I would have thought there would be 8b/10b encoding, and perhaps some SoF / EoF / CRC bytes included too.
Why doesn't the CSI clock need to take these extra bytes into account?
Show LessCyU3PUsbSendEP0Data fail on Timeout
Hi there,
I reactive this post because with CX3 and 1.3.4 SDK I still encounter the problem. Here is the situation. We have IN transfers superspeed nearly at maximum data rate of CX3. Typically, it is more than 2 Gbits/s. we use the EP0 for (vendor) commands and thus IN transfer. These IN transfers on EP0 are very small, typically only 2 bytes returned as IN.
At a point, we get timeout code as result of CyU3PUsbSendEP0 function and after that there is NO way to retrieve the correct behavior even when IN superspeed transfers ends. I find this totally weird. There is no mean to reset this situation ?
On parallel OUT EP0 is still working, exactly as described in this post.
I tried to use the "suspend" code here described but this doesn't work because the suspend operation is not reliable and most of the time doesn't operate any suspend in DMA transfers : the gChannelSuspended variable doesn't commute to suspended state and timeout variable comes to zero itself. "Sometimes" the suspend arises but most of the time it doesn't. By the way we use auto Many to One transfers operations for the superspeed IN high data rate endpoint.
I also didn't find where the GpifToUSB code can help to understand the situation.
Is there a solution for this ? This problem seams to be present since several years now, we would be happy to solve it because this is really a HUGE problem when using CX3 and FX3.
Please give a solution for a RELIABLE EP0 RESET when timeout arises !!
Thank you
Best Regards.
Show Less