This may have been placed in the wrong area but I am sure that will get figured out.
As the title says we are developing on a Cypress CX3 chip that we are viewing issues on that has been designed to be used as a camera board with 2 LED's. The board is set up with a USB-C connector. We are attempting to have a powered usb hub connect to the device and allow the host computer to trigger the hub to power up and stream images. However during a specific power up sequence the camera device will get locked into an unknown state and be unable to stream images. However we are able to see the device in the tree and still issue vendor commands.
How to reproduce the problem:
Using a powered hub we are able to 100% reproduce the issue by using the following steps ONLY with usb C to C cables. We cannot reproduce with C to A:
1. plug device into UNPOWERED USB hub w/ usb C to usb C cable
2. plug hub into UNPOWERED laptop w/ usb C to usb C cable
3. plug in power to usb hub
3. power on laptop
Data and information collected:
1. The device appears to get some sort of power to the CX3 chip on the order of 80mV and we have an LED attached to the device reset call that *appears to attempt to start a reset but does not complete*. This is an assumption. During normal operation we would have the laptop turned on. We would plug the device into the laptop and see a full white LED pulse and have the device do its reset.
2. Issuing a hard reset over I2C will reset the device and fix the issue. But we need to find out what is causing the issue and prevent it or understand why it is happening
3. Connecting UART into the device during the initial start up allows me to see the following dma errors:
4. Attempting to manually initialize the device through the API calls for the mipi and device initialization via a vendor command does not fix the issue.
5. Placing delays in the startup of the code does not prevent the initial startup from happening during power up of the hub
Any help or insight into how we could potentially get closer to our solution would be very appreciated. Thank you for your time and please let me know if I can provide any additional information to provide a more clear description of our issue.
I am trying to read from a Mfi chip through i2c using the FX3 SuperSpeed Explorer Kit. The transaction fails. I attached a scope capture showing a read of the mfi chip internal address 0x03. It looks like the chip is setting a short nak after the chip address (0x20). The FX3 i2c peripheral does not seem to care and the nak duration seems to be too short.
Do you have sample code that successfully reads or writes to a mfi chip?
I've got problem with DMA watermark flag for write transfer. From the very beginning it is in it's initial state (active low and initial low), when as per my understanding it should go to low state after I fill buffer with some data. Could it be I have to adjust watermark value in my firmware? Below I attach screen from chip scope.
My FPGA is monitoring state of that flag and when it's changes it state to low allows to write few more words to Fx3 device (based on watermark value in my case watermark is 3)
I've double check my FPGA is monitoring right port (flag uses GPIO21 witch is CTL4 signal in Fx3, G25 in interconnection board).
state machine I use: SyncADMUx(16bit data bus 7bit address bus)
firmware: slave fifo (AN65974; with 2 isochronus endpoint)
I use xilinx FPGA (SP605), and cypress cyusb3-001 kit.
Here is the thing that I 've bought an CYUSB3KIT-003,and I used it in slave fifo mode. I used FLAGA and set it to gpio_21. As I understand it, gpio_21 is connected to the CTL_4 pin of the board so it should be logic 0 after the board is booted, however , its voltage was about 0.9V.
How is it happen?Show Less
Attached is part of my FX3 state machine when doing READing Data and the interface timing I suppose FX3 would be.
State machine will go from READ state to RD_WAIT state triggered by rfifo_empty(from external device:FPGA).
my question is :
If I just want to read 4 times, but state machine will go to RD_WAIT(slcs/slrd/sloe==HIGH) after it samples rfifo_empty==HIGH at positive edge of PCLK. If the interface timing is like what I draw, there will exist 5 read transfers.
How to avoid this situation? (Or maybe my assumption about interface timing is not correct)
For my project, I'm currently using the FX3 (CYUSB3014) and looked into the SPI GPIO bit banging example as reference for the bit banging approach and given my timing requirements, it seems that we would need a delay less than a microsecond in between bits. From the looks of it, the smallest delay that can be used is with the CyU3PBusyWait (1uS). Is it possible to sample the logic levels of the GPIO pin/s with smaller delays and perform bit banging at a faster rate?
When I was learning and using the CYAPI library, I found a problem.
About BeginDataXfer and FinishDataXfer. In these 2 functions, they all need a buffer paramemter.
So I checked the source code. In BeginDataXfer function, the buffer will be memcpy into pXmitBuf.
And in FinishDataXfer, the buffer will be memcpy out from pXmitBuf.
So why do we need such a weird repetitive operation?
Hello cypress community,
I'm using Fx3 for my product development.
I have 2 versions of Src Codes : 1. with Library 1.3.3 version, 2 with library 1.3.4 version
I've a total of 3 threads running
1. USB Rx thread -> which will be triggered when respective USBevent is set when USB bulk out data is received .
2. Timer thread
3. GPIO therad that will be awake when an GPIOevent is set when respective GPIO gets triggered.
Now My sequence goes like this -> I send USB data on Bulk-out endpoint so that some events will get triggered and threads wokeup as expected and the data will be handled as required. I can do this exercise seamlessly without any issues using 1.3.3 library, but If I use 1.3.4 Library source code I see that USB Rx event is not being set and therefore Fx3 is not able to get any data over BULK-out endpoint.
This weird behavior happens everytime when I use 1.3.4 library, and try to send data continuously within ~1 sec frequency.
Is this expected (i believe not), Can I know the differences with two libraries that can cause this sort of behavior. I have gone through release notes of 1.3.4 library but unable to find any relevant information.
I say that events are not triggered based on the logs that I implemented in FW.
will be waiting for your responses.
Thanks and regards,
I'm a newbie so my question might sound trivial.
I'm trying to get my ARM-USB-TINY-H to debug through jtag a cypress FX3 on a custom board.
I've succeeded to flash out an example to the FX3 using the USB3 connection, but it doesn't have debug capabilities.
can anyone point me to the right direction on how to get it to work?Show Less
这个FX3固件是把FX3的SPI flash中的bit文件下载到lattice FPGA运行，FX3 GPIF口是被配置成FPGA的slave fifo的，同时FX3在上位机上被枚举成一个UVC标准设备，怎样将它改到Xilinx zynq开发板上运行，并且FPGA的bit文件不用放在FX3的SPI器件中，直接存放在FPGA开发板上？谢谢Show Less