USB superspeed peripherals Forum Discussions

Hi,

what is the best example to use (spi regmode or spi dmamode) for setting up a CMOS sensor that uses SPI interface. Is there any code examples available setting up an SPI interface when using a LUPA-300 in parallel output without using an FPGA? This will mainly work in snapshot mode. Still in the process of learning how to program this type of device. Any help much appreciated.

Two CYUSB3KIT-003 are stack connected and the firmware are downloaded to RAM and 8KB file is transfered successfully as 001-87216_AN87216_Designing_a_GPIF_II_Master_Interface.pdf described.

I opened two Streamer.exe are opened, one choose master devices' BULK OUT, anoter choose slave devices's BULK IN and start transfer on both, there is almost no bandwidth and most packet are timeout.

How to test the bandwidth of this configuration?

Hello,

I have to transfer data from FX3 to FPGA using GPIF II Interface.

here Producer Events are generating but Consumer Events are not generating.

Please find the firmware and GPIF file attached below.I need your help very badly.

Best regards,

Aswini

Hi,

I see in the FX3 TRM that the CX3 has weak internal pullups, but there's no API (that I found) to enable them.  How is this done?

Thanks,

Scott

Hi,

I have to  transfer data from FX3 to FPGA  using GPIF II interface.I'm using the firmware that is in  AN65974 and i will give data through control center.But i'm able to receive only starting 2 bytes,the remaining bytes are missing,as shown in below snapshot.What may be the reason for this,kindly anyone  let me know the issue.

Regards,

Aswini

In CYUSB3KIT-003 the VBUS pin of FX3 is connected to the output of U11.

Then when J3 is removed and VBUS pin of FX3 will depends on external power state instead of VBUS from USB connector.

Will this have problem when the host PC change power states and can the firmware be modifired to deal with this problem?

I have changed the firmware provided AN75779 to meet the requirement with the follow features :

1. 32-bit synchronous parallel data interface

2. 16 bits per pixel

3. YUY2 color space

4. 3264*2448 pixel resolution

5. 16 frames per second

6. Active high frame, line valid signals.

I don't know why streaming is not working.

I hope someone could help me, thank you.

What is the process to use DMA to transfer data to parallel bus from a CPU on FX3?

Already tried with success:

- USB socket to CPU interfaces using MANUAL_OUT and MANUAL_IN.

- Parallel Port Socket to USB socket interfaces using MANUAL operation.

- DMA fabric on the FX3 chip to accomplish a lot of high speed USB 3.0 transfers.

- DMA fabric to ping-pong outgoing DMA traffic to a USB endpoint similar to the UVC (AN75779) example.

- Slave Fifo example (AN65974) for the Xilink Spartan 7 board with a Super Speed Explorer board.

A CPU can be used to Commit the buffer and see the DMA Flags for the socket change.

Trying to read the parallel port socket, no data appears on the bus.

Why would this work differently than if a USB socket is initiating the DMA conversation in MANUAL?

Greg

Hello,

We are looking into using the FX3 to connect up to 4 image sensors together using LVDS.

Each camera is potentially a 1 lane LVDS, grey scale 8 bit sensor with 640 x 480 resolution at 100 FPS, which is about 1 Gbps. This should in theory be low enough for USB3.1. Optimally we want to obtain 4 different images, but if that is not possible, one large combined image, which we can separate later our self is also acceptable.

It it possible LVDS-wise, to connect up to 4 sensors at this speed on the FX3?

At this point, is there any other complications that can be foreseen using this concept?

If there is another chip we are not aware of, which can do this, we are also interested in that.

Regards

Nicolai C.

I am driving the CX3 input by a MIPI video stream @2560x720p @25 fps (1 data lane, CSI clock @496MHz)

The MIPI stream is generated by a pair of sensors @1280x720p merged by a Lattice FPGA with mip2csi IP to get the CX3 input.

The configuration is successfully performed (with the obvious error that this will not work with USB 2.0) and the YVC CX3 is enumerated correctly. The FPGA is under debug so far ...

I am using the UVC Troubleshooting Guide – KBA226722  as a reference, still I would like to know in advance if the community can suggest if there are any issue

Thanks much