USB superspeed peripherals Forum Discussions

Hello,

I´m searchnig for solution how to convert MIPI C-PHY 1.0 camera signal (sony imx 586 trial lanes) to HDMI, have Infineon some solution like CYUSB3065 but with HDIM output ?  Or i must do it through some FPGA or ? 

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你好 我做了5块板子 用的3014 ，第一次上电 只有一块板子 可以正常启动，正常烧写ram 和 flash  ;  2块板子 PC上完全识别不了 ；  2块板子 ，PC能识别到 ，烧写ram是可以的 ，但是烧写Flash 失败  ；用 USBBulkSourceSink.img 这个固件烧写ram ， C++ Stream 软件里面也不能识别Endpoint   ； 

请问有可能是哪些原因造成的 硬件上该怎么排查 

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Hi ,

I am using the FX3 with FPGA and it works properly when i send 1024 byte from PC -> FX3 -> FPGA and received 1024 byte from FPGA -> FX3 -> PC with the sync slave fifo mode 16 bit data bus.

As i would like to send a large amount of data e.g. from sensor -> FPGA -> FX3 -> PC.

dmaCfg.size = size; // which is 1024 when it is super speed.

therefore, once i send 1024 byte, the full flag will asserted and need to wait until i received the data and send the next. It will become slow if i use this method.

Therefore, i try to modify dmaCfg.size = 16384;  Then, i can send the data continuously from FPGA and it looks good.

*i am using the CY_U3P_DMA_TYPE_MANUAL

However, even i send a command with  function bool outEndpoint.XferData(ref outData, ref xferLen), i need to fill in 16384 byte, then it will send it out. 

Is there any solution that i can send e.g. 1024 byte, FX3 will also send out the data and do not need to fill in the whole dmaCfg.size. As i only need to use the large buffer when i stream the data from sensor to FX3.

Thanks

 

Paul

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Dear ifx teams: 1、usb的并口控制信号，就是USB_PHY_CTL【0-12】组内等长，误差±5mil；usb的并口数据，就是USB_PHY_DQ【0-31】组内等长，误差±5mil，这个等长合理吗？ 2、USB_PHY_CLK和数据线等长还是和控制线等长？ 3.并口的阻抗需要控制吗 --- AN70707 page 14 ，讲的不是很清楚，谢谢指导！ Show Less

Hello,

I am starting work with FX3 chipset, and follow appnote AP75705 example USB Bulk Loop Auto.

I have compile the code; Program the board  via "Control center", I am having problem when trying to perform BULK transfer,

once I hit button "Transfer data Out" I am getting error 997:

BULK OUT transfer
BULK OUT transfer failed with Error Code:997

I have search support  forums and find two similar topics:

https://community.infineon.com/t5/USB-superspeed-peripherals/BULK-OUT-transfer-failed-with-Error-Code-997-while-transfering-file-above-4MB/td-p/94626

https://community.infineon.com/t5/USB-superspeed-peripherals/BULK-IN-transfer-failed-with-Error-Code-997/td-p/58096

I have tried to update driver on PC, didnt help.

I wasnt clear about how to change "endpoint timeout" at control center application, suggested in one of the postings above.

Also, if there is anything else what can be done to get the application up running, please advise at your earliest convenience.

 

Regards,

 

Stalker  

 

 

 

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Hi All,

am working on ar1820 sensor  with CX3 controller .

 here taking raw firmware in 10 bits of depth.

it's working fine on some boards exactly out of 10, 5 are working boards and 5 are not working for the boards.

Settings Details:
4 lane - 576Mbpl[MIPI Clock]
24line -  96Mhz[Parallel Clock]

resoution - 4912x3684@9fps.

debugging steps:
1. checked error register on Toshiba 

MIPI-CSI Protocol and Physical Layer Errors in CX3... - Infineon Developer Community

it looks Multi-Data Lane Sync Byte Error Count and Unrecoverable Packet Header Error .
thing is Lane sync error happens in lanes 2 and 3 alone.
 
is there a Lane alignment register present in the Toshiba? or any related solutions?

Thanks for your effort in this matter.

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I am working on a project where we would like to connect an ADC directly to the FX3 and send to the host only alternate samples (i.e. every other sample); for instance the GPIF II PCLK would be running at 100MHz, but the samples sent to the host would be at a rate of 50MHz.

Is this possible using the GPIF II state machine? If so, do you know of a similar project to see how they did it (without using an FPGA)?

Thanks in advance,

Franco

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