USB superspeed peripherals Forum Discussions
When use Master/Slave example in AN87216 to constantly transfer data between two CYUSB3KIT-003 (from master to slave) with two custom C# programs, sometimes (sometimes after seconds, sometimes after a very long period) the transfer stalls - at this time, even with Control Center, the slave bulk IN and bulk OUT endpoints doesn't respond (timeout after 2secs) , control endpoint OUT return error code 997 immediately.
The problem is not in the C# program since it can work for very long time and Control Center can't send/receive data too after the pair is dead.
The master also doesn't respond to OUT but the reason may be buffer full after slave "dead".
The master doesn't respond to IN but the reason is at least that there is no data in the master IN buffer since only the slave can send data to master but in the experiment only master send data to slave, and after the slave is dead, there is noway to send data to the master.
Abort Pipe and Reset Pipe button in Control Center doesn't resolve the problem, only device reset works.
There is no serial port message since there is no code that send messages - where to insert some print code?
How to debug this situation?
How to know what is the status of the slave device?
How to bring the slave back as fast as possible?
Could there be any bugs in the firmware?
Show LessI want to develop a linux driver for this platform running my firmware.
Hardware : CYUSB3KIT-003
Development cycle :
1) Build and binary elf or img (elf2img)
2) test in the board by:
- Flashing to the I2C memory using usb3 or jtag, and boot from i2c
OR
- Boot from USB3 using some command line tool and re-enumerate to show my firmware capabilites
How Can I develop a firmware , flash it and test using linux ?
Now I'm using ubuntu 16.04.
Thanks
Lucas
Show LessThey are thinking that interlaced design based on AN75779. And, they would like to confirm that the following specifications are feasible.
However, the project of AN75779 does not include the project created by CX3 Configuration.
[Spec]
MIPI : 148.5MHz 2lane
H-Active、 38.79us (38.79usx148.5MHz/4= 1440pix)
H-Blanking、 24.77us (=63.56us-38.79us)
V-Active、 odd/even:243/242
V-Blanking、 20/21 (or 19.5/20.5?) ?
Frame Rate、 30fps
THS-Prepare、~100ns
THS-Zero ~250ns
Q)
Why AN75779 did not include the CX3 configuration project, is there any reason for that?
Assuming that using only conformance is checked with CX3 Configuration, Is it feasible to apply the settings to cyfxuvcdscr.c directly to reflect the actual FW?
Best Regards
Arai
Show Less有个项目需求看下cypress是否有相关芯片。
项目需求:板卡接收2路SDI 原始视频信号,需要将SDI视频信号传给GPU做图像处理,视频格式Yuv422.
- 1. GPU视频接口为MIPI CSI-2, 想问下cypress是否有SDI转MIPI的转换芯片。
- 2. 我看Cypress 的CYUSB306X, 有将MIPI接收转换为USB输出的SOC, 想问下是否有类似的SDI接收转换为USB输出的SOC。
谢谢
Show LessWe are trying to embed CyAPI.lib in a Qt project and get these errors when trying to link:
Some questions:
- How do we solve this?
- Is the CyAPI.lib compiled with Visual Studio?
- Is the CyAPI.lib meant to be usable in Qt/mingw?
- Do you have a static lib for Qt/mingw?
We also have a source code version of the CyAPI.lib, that we have added to our Qt project.
But the source code doesn’t match the CyAPI.lib that we have, and has an error that we have difficulties to work around.
When using the CyAPI.lib in a VS project, we don’t have the error (this way we conclude that source code and CyAPI.lib don’t match).
- Could we get the latest source code of the CyAPI.lib?
- Or :could we get the source code that matches the CyAPI.lib that we have right now?
Hello Everyone,
We are planning to use SPI Flash boot option for FX3 controller. As per the datasheet, SPI flash/EEPROM devices from 1 Kb to 32 Mb in size are supported for boot.
Note that SPI boot has been tested with the part numbers M25P16 (16 Mb), M25P80 (8 Mb), M25P40 (4 Mb), W25916, and MX25L1606L, but the equivalents of these parts may also be used.
Most of these selected parts are not active. Please suggest other SPI Flash supported with FX3 controller.
Also, please check and let us know if we can use W25Q80DVSNIGCT (Winbond SPI Flash) with FX3 controller for the booting purposes.
Thanks & Regards,
Sunny Watts
Show LessHello,
I have some configuration problems when using the cx3 with a custom camera board.
More specifically, I have Mipi problems when configuring the CX3 with 4 Tx lanes receiving RAW8 data. Before going into details, I just want to anticipate the following:
-between camera and cx3 I have an FPGA stage where I convert the parallel pixel into serial (CSI-2), hence I can reconfigure the data format.
-The cx3 successfully worked with 2 Tx lanes for both RAW10 and RAW8 format (I set the GPIF bus width to 16 in both cases as explained in several threads, otherwise e-camview wouldn't work with a GPIF bus width set to 8).
-The cx3 successfully worked with RAW10 format configured with 4 TX lanes (meaning that I don't have routing problems with 4 TX lanes).
The parameters I am using are the the following:
- CSI clock 80 MHz
- 4 data lanes
- non-continuous clock mode
- Pixel clock 80.0 MHz
- Video format: RAW8
- Resolution: 1024x200
- H-blanking: 2152
- V-Blanking: 73
- FPS: 88
- THS prepare 100 ns, THS-zero 150 ns.
This is how I configured the CX3:
CyU3PMipicsiCfg_t Camera_control =
{
CY_U3P_CSI_DF_YUV422_8_0, /* CyU3PMipicsiDataFormat_t dataFormat */
4, /* uint8_t numDataLanes */
1, /* uint8_t pllPrd */
79, /* uint16_t pllFbd */
CY_U3P_CSI_PLL_FRS_250_500M, /* CyU3PMipicsiPllClkFrs_t pllFrs */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t csiRxClkDiv */
CY_U3P_CSI_PLL_CLK_DIV_4, /* CyU3PMipicsiPllClkDiv_t parClkDiv */
0, /* uint16_t mClkCtl */
CY_U3P_CSI_PLL_CLK_DIV_2, /* CyU3PMipicsiPllClkDiv_t mClkRefDiv */
1024, /* uint16_t hResolution */
300 /* uint16_t fifoDelay */
};
I also add the following picture from the config file to confirm that I do not have errors:
I configured it in order to append 8 bits of zero to each RAW8 pixel (through CY_U3P_CSI_DF_YUV422_8_0) and to have a number of bytes per frame equal to 1024x200*2bytes= 409600 bytes. This operation properly worked when the system was configured with 2 Tx lanes.
I also used the phy time delay API properly.
When I run e-cam view the error I get on the UART port is the following:
As you can see I constantly have crc errors and I think this is related to how I configured the MIPI interface. I'm not able to constantly receive a full frame. Do you have suggestions on where the problem could be?
Thanks in advance.
Show LessHello!
I'm looking for the source code for cyfwstorprog as the board I have is a custom FX3S and uses different GPIO's to the standard set by the SDK.
I'm also wondering if it's possible to encrypt emmc content, and whether general content on the emmc chip itself can be encrypted from the SIB interface?
The firmware example for MSC does not pass through the CPU, so I was wondering what options there are to protect data in the EMMC and still maintain a high speed?
Regards!
Fujimi
Show LessHi,
I'm using cyfxusbi2sdmamode.c example. It configures uart and i2s.
Where this uart is located ?
- Some virtual uart through USB3 cable into my Host ?
- Or it the one exposed by micro usb jtag cable ?
The code says:
/* Configure the IO matrix for the device. On the FX3 DVK board, the COM port
* is connected to the IO(53:56). So since we need to use both I2S and UART,
* configure the GPIF bus to be 32 bit. This does not mean that the GPIF has
* to be in 32 bit configuration, it just means that the whole 32bit shall be
* reserved for the GPIF interface and not available for GPIO. Another option
* is to not use UART, and use I2S_ONLY mode or use an external UART controller
* on the IO(46:49). */
Where is this IO(53:56) ? Can you explain what is IO(53:56) ?
Looking at "SuperSpeed Explorer Kit Schematic.pdf" I can't find IO(53:56).
Show LessHello
[System] NTSC ⇒ Decoder ⇒ CX3 ⇒ PC
The active pixels output by the Decoder are as follows.
- H-Active: 1440
- V-Active: 240
They are thinking that H-Active contains two lines of data when importing interlace,
Question) Regarding the MIPI capture settings (Image Sensor Configuration screen) on the CX3, is it possible to import as 720x480 by doing as following?
H-Active : 720
V-Active: 480
Or, the MIPI side sets the capture as 1440 × 240, Is the setting of the descriptor on the UVC side 720x480?
MIPI side
H-Active: 1440
V-Active: 240
UVC side descriptor setting
720 × 480
Best Regards
Mac
Show Less